Verilog-AMS

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Verilog-AMS is a derivative of the hardware description language (HDL) Verilog (IEEE 1364-1995 Verilog HDL). It includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems.

The Verilog-AMS standard was created with the intent of enabling designers of analog and mixed signal systems and integrated circuits to create and use modules that encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components [1,2,3].

Verilog-AMS is an industry standard modeling language for mixed signal circuits. It provides both continuous-time and event-driven modeling semantics, and so is suitable for analog, digital, and mixed analog/digital circuits. It is particularly well suited for verification of very complex analog, mixed-signal and RF integrated circuits[4].

Contents 1 See also 2 References 3 External links 3.1 General

[edit] See also

• Verilog
• Verilog-A
• VHDL

[edit] References

• [1] Accellera Verilog Analog Mixed-Signal Group, "Overview," http://www.verilog.org/verilog-ams/htmlpages/overview.html.
• [2] Verilog-AMS Language Reference Manual
• [3] The Designer's Guide to Verilog-AMS
• [4] Verification of Complex Analog Integrated Circuits
• [] I. Miller and T. Cassagnes, "Verilog-AMS Eases Mixed Mode Signal Simulation," Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems, pp. 305-308, Available: http://www.nsti.org/publ/MSM2000/T31.01.pdf

[edit] External links

[edit] General

• Accellera Verilog Analog Mixed-Signal Group
• verilog-ams.com
• The Designer's Guide Community, Verilog-A/MS — Examples of models written in Verilog-AMS