Turion 64

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Turion 64 is the brand name AMD applies to its 64-bit low-power (mobile) processors. The Turion 64 and Turion 64 X2 processors compete with Intel's mobile processors, initially the Pentium M and currently both of the Intel Core processors.

Turion 64 processors are compatible with AMD's Socket 754 and are equipped with 512 or 1024 KiB of L2 cache, a 64-bit single channel on-die memory controller, and an 800MHz HyperTransport bus. Battery saving features, like PowerNow!, are central to the marketing and usefulness of these CPUs.

Contents

[edit] Features

[edit] Turion 64 "Lancaster" (90 nm)

All models support:

[edit] Turion 64 "Richmond" (90 nm)

The models support the same features available in Lancaster, plus AMD Virtualization.

[edit] Future roadmap

In the first half of 2007, Hawk[1] will update the current Turion 64 X2, adding support for DDR2-800 . This move will set it up directly against the a new Intel Santa Rosa platform for the Core 2 Duo "Merom" which also supports DDR2-800. Simultaneously, AMD will unveil a refresh of its Kite platform[2] which brings Wireless Draft-N support, HDMI, hybrid hard drives and dynamic graphics switching to its recommendations. The feature to look out for will be dynamic graphics switching which will seamlessly switch between discrete graphics to maximize performance or low-power integrated graphics to extend battery life.

Griffin[3] is a future Turion 64 processor featuring Hypertransport 3.0, a new low-power core featuring split-power planes and DDR2-800 support[4].

[edit] Model naming methodology

The model naming scheme does not make it obvious how to compare one Turion with another Turion, or even an Athlon 64. The model name is two letters, a dash, and a two digit number (for example, ML-34). The two letters together designate a processor class, while the number represents a PR rating. The first letter is M for single core processors and T for dual core Turion 64 X2 processors. The later in the alphabet that the second letter appears, the more the model has been designed for mobility (frugal power consumption). Take for instance, an MT-30 and an ML-34. Since the T in the MT-30 is later in the alphabet than the L in ML-34, the MT-30 consumes less power than the ML-34. But since 34 is greater than 30, the ML-34 is faster than the MT-30.

[edit] Cores

[edit] Lancaster (90 nm SOI)

  • L1 cache: 64 + 64 KiB (data + instructions)
  • L2 cache: 512 or 1024 KiB, fullspeed
  • MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, PowerNow!, NX Bit
  • Socket 754, HyperTransport (800 MHz, HT800)
  • VCore: 1.00V - 1.45V
  • Power consumption (TDP): 25/35 Watt max
  • First release: March 10, 2005
  • Clock rate: 1600, 1800, 2000, 2200, 2400 MHz
    • 25W TDP:
      • MT-28: 1600 MHz (512 KiB L2-Cache)
      • MT-30: 1600 MHz (1024 KiB L2-Cache)
      • MT-32: 1800 MHz (512 KiB L2-Cache)
      • MT-34: 1800 MHz (1024 KiB L2-Cache)
      • MT-37: 2000 MHz (1024 KiB L2-Cache)
      • MT-40: 2200 MHz (1024 KiB L2-Cache)
    • 31W TDP:
      • MK-36: 2000 MHz (512 KiB L2-Cache)
    • 35W TDP:
      • ML-28: 1600 MHz (512 KiB L2-Cache)
      • ML-30: 1600 MHz (1024 KiB L2-Cache)
      • ML-32: 1800 MHz (512 KiB L2-Cache)
      • ML-34: 1800 MHz (1024 KiB L2-Cache)
      • ML-37: 2000 MHz (1024 KiB L2-Cache)
      • ML-40: 2200 MHz (1024 KiB L2-Cache)
      • ML-42: 2400 MHz (512 KiB L2-Cache)
      • ML-44: 2400 MHz (1024 KiB L2-Cache)

[edit] See also

[edit] References

[edit] External links