Signal integrity

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Signal Integrity, sometimes known as SI, refers to electronic circuit tools and techniques that ensure electrical signals are of sufficient quality for proper operation. Alternatively, Signal Integrity tools attempt to identify and remove effects that cause a design to malfunction due to distortion of the signal waveforms. In integrated circuits, or ICs, the main cause of signal integrity problems is noise induced by neighboring connections, or crosstalk. In CMOS technologies, this is primarily due to coupling capacitance, but in general it may be caused by mutual inductance, substrate coupling, non-ideal gate operation, and other sources. Induced noise can have many drastic consequences for digital designs:

  • it can make the design work incorrectly in some cases, or even fail completely
  • it can make the design slower than planned
  • it can create yield problems.

The cost of such a failure is very high, and includes photomask costs, engineering costs, and opportunity cost due to delayed product introduction. Therefore electronic design automation tools have been developed to analyze, prevent, and correct these problems.

Signal Integrity affects all levels of electronics packaging, including but not limited to the IC. For high-speed digital products, at the level of an IC package or printed circuit board (pcb), the main issues of concern are ringing, crosstalk, ground bounce, and power supply noise. Without due consideration of these basic issues, typical high-speed digital products can fail to operate at the design stage or, worse yet, become flaky or unreliable in the field.

Contents

[edit] History

Signal integrity primarily involves the electrical performance of the wires and other packaging structures used to move signals about within an electronic product. Such performance is a matter of basic physics and as such has remained relatively unchanged since the inception of digital computing devices. Products as old as the Western Electric crossbar telephone exchange (circa 1940), based on the wire-spring relay, suffered effects akin to the ringing, crosstalk, ground bounce, and power supply noise that plague modern digital products.

In the early days of the modern VLSI era, digital chip circuit design and layout were manual processes. The use of abstraction and the application of automatic synthesis techniques have since allowed designers to express their designs using high-level languages and apply an automated design process to create very complex designs, ignoring the electrical characteristics of the underlying circuits to a large degree. However, scaling trends (see Moore's law) brought electrical effects back to the forefront in recent technology nodes. With scaling of technology below 0.25 µm, the wire delays have become comparable or even greater than the gate delays. As a result the wire delays needed to be considered to achieve timing closure. In nanometer technologies at 0.13 µm and below, unintended interactions between signals (or noise) became an important consideration for digital design. At these technology nodes, the performance and correctness of a design cannot be assured without considering noise effects.

[edit] Overview

In analog circuits, designers are concerned with noise that arise from physical sources, such as thermal noise, flicker noise, and shot noise. These noise sources on the one hand present a lower limit to the smallest signal that can be amplified, and on the other, define an upper limit to the useful amplification.

In digital circuits, noise arises not from fundamental physical sources, but from the operation of the circuit itself, primarily the switching of other signals. Higher interconnect density has led to each net having neighbors that are closer, thus leading to increased coupling capacitance between neighboring nets. As circuits shrink in accordance with Moore's law, several effects have conspired to make noise problems worse:

  • To keep resistance tolerable despite decreased width, modern wire geometries are taller in proportion to their spacing. This increases the sidewall capacitance at the expense of capacitance to ground, hence increasing the induced noise voltage (expressed as a fraction of supply voltage).
  • Technology scaling has lead to lower threshold voltages, and has also reduced the headroom between threshold and supply voltage, thus reducing noise margins.
  • Logic speeds, and clock speeds in particular, have increased significantly, thus leading to faster transition times. These faster transition times are closely linked to higher capacitive cross talk. Also, at such high speeds the inductive properties of the wires come into play especially mutual inductance.

These effects have increased the interactions between signals and decreased the noise immunity of digital CMOS circuits. This has led to noise being a significant problem for digital ICs that must be considered by every digital chip designer prior to tape-out.

While the law of physical scaling suggests that VLSI circuits naturally operate faster when reduced in size, no such physical principle assists the IC package or PCB designer. The gross exterior sizes of these features have remained relatively unchanged since the introduction of the 8080 processor in 1974. An IC package or PCB designer increases performance not by physically shrinking, but through these techniques:

  • Placing a solid reference plane adjacent to the signal traces to control crosstalk,
  • Controlling the trace width spacing to the reference plane to create consistent trace impedance,
  • Using terminations to control ringing,
  • Providing sufficient ground (and power) connections to limit ground bounce, and
  • Distributing power with solid plane layers to limit power supply noise.

[edit] Comparison of VLSI and Printed circuit board/Integrated circuit packaging issues

One primary difference between communication within an IC and communication in a high-speed IC package or PCB environment is the circuit electrical impedance. In a high-speed IC package or pcb environment, digital signal pathways have a low impedance, meaning that the circuit impedance lies well below the 377-ohm impedance of free space. Contrast that with the typically high impedance (>377 ohms) possessed by digital IC circuits on die. As a consequence of their naturally low impedance, IC package and PCB signal traces carry much more current than their on-chip counterparts. This larger current induces crosstalk primarily in a magnetic, or inductive, mode, as opposed to a capacitive mode. To combat this crosstalk, digital PCB designers must remain acutely aware of not only the intended signal path for every signal, but also the path of returning signal current for every signal. The signal itself and its returning signal current path are equally capable of generating inductive crosstalk.

A second difference between communication within an IC and communication in a high-speed IC package or PCB environment involves the signal conductor resistance. PCB conductors, being relatively large (typically 100 um or more in width), have a small series resistance (typically 0.1 ohms/cm). On-die conductors have much more resistance.

Since it has almost negligible resistance, a PCB conductor is characterized primarily by its capacitance and inductance per unit length. Together, these properties determine the trace's characteristic impedance and delay. The trace loss (normally expressed in units of dB/cm) is determined as a second-order parameter from the trace resistance and dielectric losses associated with the pcb material. Pcb traces are frequently terminated to limit objectionable signal reflections that can bounce from end to end in what is basically a low-loss transmission line. In contrast, on-die conductors are characterized primarily by their capacitance and resistance per unit length with inductance being a second-order parameter. The losses for on-die conductors are so high that end-to-end reflections do not surface as a deleterious phenomenon. On-die conductors almost never require termination.

The delay of a well-terminated PCB trace varies in direct proportion to trace length and is not sensibly affected by drive strength. The delay of an (un-terminated) on-die conductor varies in proportion to the SQUARE of its length, according to the Elmore delay approximation for R-C mode transmission structures. The insertion of transmission repeaters can substantially improve delay in any medium, like an on-die metallization layer, that follows a square-law rule for delay, but are rarely used in a linear-delay medium, like a PCB.

[edit] Finding Signal Integrity Problems

Typically, an IC designer would take the following steps for his verification:

  • Perform a layout extraction to get the parasitics associated with the layout. Usually Worst-case parasitics and best-case parasitics are extracted and used in the simulations.
  • Alternatively (or subsequently), measure the impairment presented by the connection using high speed instrumentation such as a vector network analyzer. For example, IEEE P802.3ap Task Force uses measured S-parameters as test cases for proposed solutions to the problem of 10Gbit/s Ethernet over backplanes.
  • Accurate noise modeling is a must. Create a list of expected noise events, including different types of noise, such as coupling and charge sharing.
  • For each noise event, decide how to excite the circuit so that the noise event will occur.
  • Create a SPICE (or another circuit simulator) netlist that represents the desired excitation.
  • Run SPICE and record the results.
  • Analyze the simulation results and decide whether any re-design is required.

Modern signal integrity tools for IC design perform all these steps automatically, producing reports that give a design a clean bill of health, or a list of problems that must be fixed.

[edit] Fixing Signal Integrity Problems

Once a problem is found, it must be fixed. Typical fixes for IC problems include:

  • Driver upsizing. The victim driving cell is made stronger by upsizing.
  • Buffer insertion. In this approach, instead of upsizing the victim driver, a buffer is inserted at an appropriate point in the victim net.
  • Aggressor downsizing. This works by increasing the transition time of the attacking net by reducing the strength of its driver.
  • Wire Shielding. Shielding of Critical Nets or Clock Nets using GND and VDD shields to reduce the effect of Crosstalk. May lead to routing overhead.
  • Routing changes. Routing changes can be very effective in fixing noise problems mainly by reducing the most troublesome coupling capacitances.
  • Add a preemphasis filter to the transmitter driving cell
  • Add an equalizer to the receiving cell

Each of these fixes may possibly cause other problems. This type of issue must be addressed as part of design flows and design closure.

[edit] References

  • Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and Scheffer, ISBN 0-8493-3096-3 A survey of the field of electronic design automation. Portions of this summary were derived (with permission) from Vol II, Chapter 21, Noise Considerations in Digital ICs, by Vinod Kariat.
  • High-Speed Digital Design: A Handbook of Black Magic, by Howard Johnson and Martin Graham, ISBN 0-13-395724-1. A book for digital designers, highlighting and explaining analog circuit principles relevant to high-speed digital design.
  • High-Speed Signal Propagation: Advanced Black Magic, by Howard Johnson and Martin Graham, ISBN 0-13-084408-X. Advanced-level reference text for experienced digital designers who want to press their designs to the upper limits of speed and distance.
  • Digital Systems Engineering, by William J. Dally and John W. Poulton, 1998, ISBN 0-52-159292-5, Cambridge University Press, New York, NY, USA. Textbook on the problems of building digital systems, including signal integrity.

[edit] Further reading

  • Signal Integrity Simplified by Eric Bogatin.
  • High Speed Digital Design by Hall, Hall and Macall
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