Semiconductor device modeling
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Semiconductor device modeling creates models for the behavior of the electrical devices based on fundamental physics, such as the doping profiles of the devices. It may also include the creation of compact models (such as the well known SPICE transistor models), which try to capture the electrical behavior of such devices but do not generally derive them from the underlying physics. Normally it starts from the output of a semiconductor process simulation.
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[edit] Introduction
It is useful to briefly consider the objectives of device design, both from the system and technology perspectives, prior to going into greater detail at the physical modeling level. Figure 1b provides a simplified conceptual view of “the big picture.” This figure shows two inverter stages and the resulting input-output voltage-time plot of the circuit. Clearly from the digital systems point of view the key parameters of interest are: timing delays, switching power, leakage current and cross-coupling (crosstalk) with other blocks. The voltage levels and transition speed are also of concern. The figure also shows schematically the importance of Ion versus Ioff, which in turn is related to drive-current (and mobility) for the “on” device and several leakage paths for the “off” devices. Not shown explicitly in Figure 1b are the capacitances—both intrinsic and parasitic—that affect dynamic performance. Moreover, the power scaling which is now a major driving force in the industry is reflected in the simplified equation shown in Figure 1b — critical parameters are capacitance, power supply and clocking frequency. Key parameters that relate device behavior to system performance include the threshold voltage, driving current and subthreshold characteristics. It is the confluence of system performance issues with the underlying technology and device design variables that results in the ongoing scaling laws that we now codify as Moore’s law. With this backdrop of system performance metrics that relate to the technology perspective, we now begin the consideration of the physical (and physics-based) considerations of the MOS transistor.
[edit] Device modeling
The physics and modeling of integrated circuits can roughly be divided between the surface effects associated with MOS devices and a range of bulk junction effects that involve bipolar and associated leakage and parasitic effects. As mentioned in the introduction, CMOS transistors for ULSI now claim the lion's share of practical IC devices. In CMOS technology the bulk junction device effects are virtually all parasitic. However, bipolar technology is still preferred for some applications, (see BiCMOS for some power and RF applications) and must be considered. There are of course also issues of reliability engineering--for example, electro-static discharge (ESD) protection circuits and devices--where substrate and parasitic devices are of pivotal importance. These effects and modeling are not considered by most device modeling programs; the interested reader is referred to several excellent monographs in the area of ESD and I/O modeling [12], [13], [14].
[edit] Physics driven models and their relationship to compact models
Physics driven device modeling is intended to be accurate, but it is not fast enough for higher level tools such as circuit simulators. Therefore circuit simulators normally use more empirical models (often called compact models) that do not directly model the underlying physics. For example, Inversion-Layer Mobility Modeling, or the modeling of mobility and its dependence on physical parameters, ambient and operating conditions is arguably one of the most important dependencies both for TCAD physical models and for circuit-level compact models. For mobility modeling at the TCAD level the electrical variables are the local electric field at each point in the device (i.e. components parallel and perpendicular to the planar device surface) and the various scattering mechanisms, including their technology and ambient dependencies. By contrast, the circuit-level models represent a macroscopic approximation of the physical phenomena and parameterize the effects only in terms of terminal voltages vis a vis internal (and microscopic) electric fields. Through the electrical extraction process the two representations can be compared and calibrated.
[edit] History
The evolution of technology computer-aided design (TCAD)--the synergistic combination of process, device and circuit simulation and modeling tools—finds its roots in bipolar technology, starting in the late 1960s, and the challenges of junction isolated, double-and triple-diffused transistors. These devices and technology were the basis of the first integrated circuits; nonetheless, many of the scaling issues and underlying physical effects are integral to IC design, even after four decades of IC development. With these early generations of IC, process variability and parametric yield were an issue—a theme that will reemerge as a controlling factor in future IC technology as well.
Process control issues--both for the intrinsic devices and all the associated parasitics--presented formidable challenges and mandated the development of a range of advanced physical models for process and device simulation. Starting in the late 1960s and into the 1970s, the modeling approaches exploited were dominantly one- and two-dimensional simulators. While TCAD in these early generations showed exciting promise in addressing the physics-oriented challenges of bipolar technology, the superior scalability and power consumption of MOS technology revolutionized the IC industry. By the mid-1980s, CMOS became the dominant driver for integrated electronics. Nonetheless, these early TCAD developments (cite 1 and 2) set the stage for their growth and broad deployment as an essential toolset that has leveraged technology development through the VLSI and ULSI eras which are now the mainstream.
IC development for more than a quarter-century has been dominated by the MOS technology. In the 1970s and 1980s NMOS was favored owing to speed and area advantages, coupled with technology limitations and concerns related to isolation, parasitic effects and process complexity. During that era of NMOS-dominated LSI and the emergence of VLSI, the fundamental scaling laws of MOS technology were codified and broadly applied (cite 3). It was also during this period that TCAD reached maturity in terms of realizing robust process modeling (primarily one-dimensional) which then became an integral technology design tool, used universally across the industry (cite 4). At the same time device simulation, dominantly two-dimensional owing to the nature of MOS devices, became the work-horse of technologists in the design and scaling of devices (cite 5 and 6). The transition from NMOS to CMOS technology resulted in the necessity of tightly-coupled and fully-2D simulators for process and device simulations. This third generation of TCAD tools became critical to address the full complexity of twin-well CMOS technology (see Figure 3a), including issues of design rules and parasitic effects such as latchup (cite 7 and 8). An abbreviated but prospective view of this period, through the mid-1980s, is given in (cite 9); and from the point of view of how TCAD tools were used in the design process, see (cite 10).
[edit] References
- Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and Scheffer, ISBN 0-8493-3096-3 A survey of the field of electronic design automation. This summary was derived (with permission) from Vol II, Chapter 25, Device Modeling—from physics to electrical parameter extraction, by Robert W. Dutton, Chang-Hoon Choi and Edwin C. Kan.
[edit] See also
(1) H.J. DeMan and R. Mertens, "SITCAP--A simulator for bipolar transistors for computer-aided circuit analysis programs," International Solid-State Circuits Conference (ISSCC), Technical Digest, pp. 104-5, February, 1973
(2) R.W. Dutton and D.A. Antoniadis, "Process simulation for device design and control," International Solid-State Circuits Conference (ISSCC), Technical Digest, pp. 244-245, February, 1979
(3) R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rodeout, E. Bassous and A.R. LeBlanc, “Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE Jour. Solid-State Circuits, vol. SC-9, pp.256-268, October, 1974.
(4) R.W. Dutton and S.E. Hansen, "Process modeling of integrated circuit device technology," Proceeding IEEE, vol. 69, no. 10, pp. 1305-1320, October, 1981.
(5) P.E. Cottrell and E.M. Buturla, "Two-dimensional static and transient simulation of mobile carrier transport in a semiconductor," Proceedings NASECODE I (Numerical Analysis of Semiconductor Devices), pp. 31-64, Boole Press, 1979.
(6) S. Selberherr, W. Fichtner, and H.W. Potzl, "Miminos--a program package to facilitate MOS device design and analysis," Proceedings NASECODE I (Numerical Analysis of Semiconductor Devices), pp. 275-79, Boole Press, 1979.
(7) C.S. Rafferty, M.R. Pinto, and R.W. Dutton, "Iterative methods in semiconductor device simulation," IEEE Trans. Elec. Dev., vol. ED-32, no.10, pp.2018-2027, October, 1985.
(8) M.R. Pinto and R.W. Dutton, "Accurate trigger condition analysis for CMOS latchup," IEEE Electron Device Letters, vol. EDL-6, no. 2, February, 1985.
(9) R.W. Dutton, "Modeling and simulation for VLSI," International Electron Devices Meeting (IEDM), Technical Digest, pp. 2-7, December, 1986.
(10) K.M. Cham, S.-Y. Oh, D. Chin and J.L. Moll, Computer-Aided Desing and VLSI Device Development, Kluwer Academic Publishers (KAP), 1986.
(11) R.W. Dutton and A.J. Strojwas, "Perspectives on technology and technology-driven CAD," IEEE Trans. CAD-ICAS, vol. 19, no. 12, pp. 1544-1560, December, 2000.
(12) C. Duvvury and A. Amerasekera, “ESD: a pervasive reliability concern for IC technologies,” Proc. IEEE, vol. 81, pp. 690-702, 1993.
(13) A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, Second Edition, New York, John Wiley & Sons, 2002.
(14) S. Dabral and T. J. Maloney, Basic ESD and I/O design, New York, John Wiley & Sons, 1998
