Reiner Hartenstein

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Reiner Hartenstein (born December 18, 1934 in Berlin) is a German technical fellow and computer pioneer. He is a professor of Computer Science (Informatik) at the University of Kaiserslautern. He earned all his academic degrees, also the Ph. D. degree (Dr.-Ing.) from the EE department at the University of Karlsruhe, where, he later (in the 1960ies) worked on image processing and pattern recognition for Professor Karl Steinbuch, early pioneer and trailblazer of artificial neural networks.

In the early 1970ies Hartenstein became associate professor of Computer Science at the University of Karlsruhe, where he worked on computer architecture and hardware description languages. In 1977 he joined the University of Kaiserslautern as a full professor of the Computer Science department, an, director of the Reconfigurable Computing laboratory (Xputer Lab), where he worked on design methodologies for VLSI systems (Very Large-Scale Integration) and for electronic design automation, as well as on Reconfigurable Computing architectures and compilers. In 1981 he has been visiting professor the the University of California at Berkeley, California.

Coming back from Berkeley he founded the German multi university project for VLSI design ’’E.I.S.’’, a forerunner of the ’’EUROCHIP’’ infrastructure funded by the European Union - following the world-wide Mead & Conway revolution kicked off by Carver Mead and Lynn Conway for separating VLSI design from technology and establishing it at its own discipline, at that time providing the incubation ground of the emerging electronic design automation industry. Lynn Conway called him "The German Carver Mead".

Reiner Hartenstein is the initiator of the trailblazing Hardware description language KARL and the VLSI CAD framework having been implemented around it. In this context he has proposed to use Term Rewriting in a top-down-methodology to automatically generate VLSI designs including structured floorplan layout, from mathematical formula as a specification source. (Later this proposal has been inplemented by Mauricio Ayala-Rincon). Hartenstein's work on Hardware description languages and on Reconfigurable Computing as well as on Configware/Software-Co-Compilation are regarded as pioneering achievements. Reiner Hartenstein passes as being the initiator of the methodology des super systolic arrays ( a generalization of systolic arrays, also for coarse-grained reconfigurable architectures, as well as of the anti machine paradigm (xputer or Kress/Kung machine paradigm) for reconfigurable parallel computers which are not instruction-stream-driven: the counterpart of the von Neumann paradigm.

Hartenstein is founder of the international workshop series PATMOS on ’’Low Power Integrated Circuit Design’’ and of the international workshop series on Reconfigurable Computing Education. He is co-founder of EUROMICRO and of the international conference series FPL on FPGAs, Reconfigurable Computing and its applications. His hobby is giving keynote addresses.

1 Awards
2 Famous Quotations
3 Publications
- 3.1 Links

[edit] Awards

IEEE life fellow
FPL fellow
IFIP silver core
several „best paper awards“ and „best presentation awards“

[edit] Famous Quotations

Reiner Hartenstein has coined the terms Auto-sequencing memory (ASM), Configware, Generic Address Generator (GAG), and Super systolic array

[edit] Publications

Reiner Hartenstein has published 14 books and more than 400 technical papers. e. g. the bestseller:

1977: Fundamentals of Structured Hardware Design. A Design Language Approach at Register Transfer Language
1990: A. Hirschbiel et al.: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; Proc. InfoJapan'90, Tokyo, Japan, 1990
1991 see above: Invited reprint in: Future Generation Computer Systems 7 91/92, North Holland Publ. Co.
1993 R. Hartenstein: KARL and ABL, in J. P. Mermet (ed.): Fundamentals and Standards in Hardware Description Languages; Kluwer Academic Publishers, 1993.
1998 J. Becker, K. Schmidt et al.: Automatic Parallelism Exploitation for FPL-based Accelerators; Proc. Hawaii Int'l. Conf. on System Sciences (HICSS'98), Big Island, Hawaii,1998
2002 M. Herz et al. (invited paper): Memory Organization for Data-Stream-based Reconfigurable Computing; Proc. IEEE ICECS 2002, Dubrovnik, Croatia, 2002