Quasi Delay Insensitive
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Quasi Delay-Insensitive (QDI) circuits are a class of delay-insensitive asynchronous circuits which are invariant to (and make no assumptions about) the delays of any of the circuit's wires or elements, except to assume that certain fanouts are isochronic. Isochronic forks allow signals to travel to two destinations and only receive an acknowledge from one.
More importantly, QDI circuits are Turing-complete, while purely delay-insensitive circuits are not. Of all "useful" asynchronous design styles, QDI circuits make the fewest timing assumptions, as only the isochronic fork is assumed. In practice ensuring the correctness of an isochronic fork is trivial.
Two common design styles of QDI circuits are Delay-Insensitive Minterm Synthesis and Pre-Charge Half Buffers based circuits.
Manufactured QDI processor designs include: TITAC from Tokyo Institute of Technology, MiniMIPS from Caltech, SPA from The University of Manchester and ASPRO-216 from France Telecom.
