Physical Address Extension
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In computing, Physical Address Extension (PAE) refers to a feature of x86 processors that allows for up to 64 gigabytes of physical memory to be used in 32-bit systems, given appropriate operating system support. PAE is provided by Intel Pentium Pro and above CPUs (including all later Pentium-series processors except the 400 MHz bus versions on the Pentium M), as well as by some compatible processors such as those from AMD. The CPUID flag PAE is assigned for the purpose of identifying CPUs with this capability.
The processor hardware is augmented with additional address lines used to select the additional memory, and 36-bit page tables, but regular application software continues to use instructions with 32-bit addresses and a flat memory model limited to 4 gigabytes. The operating system uses PAE to map this 32-bit address space onto the 64 gigabytes of total memory, and the map can be and usually is different for each process. In this way the extra memory is useful even though regular applications cannot access it all simultaneously.
For application software which needs access to more than 4 gigabytes of memory some special mechanism may be provided by the operating system in addition to the regular PAE support. On Microsoft Windows this mechanism is called Address Windowing Extensions (AWE), while on Unix systems a variety of tricks are used, such as using mmap() to map regions of a file into and out of the address space as needed, none having been blessed as a standard.
AMD introduced the NX bit as an additional feature of PAE mode in the AMD64 microarchitecture. Windows XP SP2 and later runs in PAE mode by default on systems with NX support in order to make use of the feature.
[edit] Page table structures
In traditional 32-bit protected mode, x86 processors use a two-level page translation scheme, where the register CR3 points to a single 4K-long page directory, which is divided into 1024 4-byte entries that point to 4K-long page tables, similarly consisting of 1024 4-byte entries pointing to 4K-long pages.
Enabling PAE (by setting bit 5, PAE, of the system control register CR4) causes major changes to this scheme. By default, the size of each page remains as 4K. Each entry in the page table and page directory is extended to 64 bits (8 bytes) rather than 32 to allow for additional address bits; the table size does not change, however, so each table now has only 512 entries. Because this allows only a quarter as many entries as the original scheme, an extra level of hierarchy must be added, so CR3 now points to the Page Directory Pointer Table, a short table which contains pointers to 4 page directories.
Additionally, the entries in the page directory have an additional flag, named 'PS' (for Page Size). If this bit (bit 7) is set to 1, the page directory entry does not point to a page table, but a single large page (2MB in length).
The NX bit is another flag in the page directory to mark pages as "No eXecute".
