PDP-11

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PDP-11/40 with dual DECtape drives.
PDP-11/40 with dual DECtape drives.

The PDP-11 was a series of 16-bit minicomputers sold by Digital Equipment Corp. in the 1970s and 1980s. The PDP-11 was a successor to DEC's PDP-8 computer in the PDP series of computers. It had several uniquely innovative features, and was easier to program than its predecessors. While well-liked by programmers, it was replaced in the mid-range minicomputer niche by the VAX-11 32-bit extension of the PDP-11. Much of the market for both machines would be taken by personal computers, including the IBM PC and Apple II, and workstations, such as those from Sun Microsystems.

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[edit] Unique features of the PDP-11 Series

[edit] Instruction set

Programmers liked the PDP-11 design because it had a highly-orthogonal instruction set which allowed a programmer to separately memorize all of the operations and the methods of accessing operands. They could then predict that any access method (or "addressing mode") would work with any operation; they did not have to learn a list of exceptions or special cases in which an operation had a special or restricted set of addressing modes.

A popular but false folk myth is that the instruction set architecture of the PDP-11 influenced the idiomatic use of the C programming language. Supposedly, the register increment and decrement addressing modes correspond to the --i and i++ constructs in C. If i and j were both register variables, an expression such as *(--i) = *(j++) could be compiled to a single machine instruction. A further claim is that the lack of different opcodes for single and double floating point operations resulted in the omission of the single precision operations in the language. Dennis Ritchie unambiguously contradicts this folk myth.[1]

In some logical sense, the set of addressing modes provided one "basis", and the set of operations provided another. Each two-operand instruction was separated into two six-bit operand identifiers (each consisting of a three-bit register number, and a three-bit addressing mode) and a four-bit op-code; single-operand instructions had one six-bit operand identifier, and a ten-bit op-code. All op-codes operated with any operand identifier address mode (or combination of them, for the two-operand instructions). Of the 8 registers (numbered 0 through 7), 7 were general-purpose and could be used for most purposes, although register 6 was specially recognized by the hardware as the stack pointer for some instructions; register 7 was the program counter. This latter innovation, together with some of the addressing modes, provided constants, absolute addresses, and relative (position independent) addressing.

16-bit words were stored little-endian with least significant bytes first. 32-bit words were often stored in an unusual middle-endian format. Due to the popularity of the PDP-11, this format is still sometimes referred to as pdp-endian.

[edit] No dedicated I/O bus

In the most radical departure from other, earlier computers, the PDP-11 had no dedicated bus for input/output; it had only a memory bus called the Unibus. All input and output devices were mapped to addresses in memory, so no special I/O instructions were needed. The interrupt system was intentionally designed to be as simple as possible, while ensuring that no event in an interrupt sequence could be missed. A device would request an interrupt by asserting a common input into one of four priority lines; the processor would respond over an interrupt daisy chain grant line, one for each priority level. (A daisy chain is a sequence of logic gates arranged in series to order events. Generally the first logic gate has first access to the grant. The daisy chain order established the order of the devices at that priority level.)

In the case of the PDP-11 design, this meant that the interrupt grant order was determined by how close the physical hardware was to the CPU on the bus. When the CPU responded, the device would place its vector address on the bus; this was the address of a 4-byte block of memory. The CPU would then load the status register and program counter from the vector table; the new contents of the status register would generally temporarily disable interrupts. The address in the program counter would be the starting address of the code to run for the interrupt. The interrupt code would then service the device, and in the process, write to the interrupting device to re-enable the interrupt signal. Finally, a special RTI (return from interrupt) instruction would return the CPU to where it was before the interrupt (which might have been in a lower-priority interrupt). Note that this process prevents loss of interrupts; at every stage, if the interrupt is not serviced, it remains in place, to be sensed on the next cycle. If a sequence were erroneously started (as from a defective device controller), the CPU would time out, generating a special spurious interrupt; the spurious interrupt would warn users of bad hardware.

[edit] Designed for mass production

Finally, the PDP-11 was designed to be produced in a factory by semiskilled labor. All of the dimensions of its pieces were relatively non-critical. It used a wire-wrapped backplane. That is, the printed circuit board plugged into a backplane connector. The backplane connector had terminals that could be connected to by wrapping wires around them. The terminal would cut the insulation around the wire and bite into the wire to form a gas-tight (i.e. corrosion-proof, therefore reliable) connection. The connector blocks were very similar to telephone connection blocks.

[edit] The LSI-11

The LSI-11 (PDP-11/03) was the first PDP-11 model produced using large-scale integration; the entire CPU was contained on 4 LSI chips made by Western Digital (the MCP-1600 chip set). It used a bus which was a close variant of the Unibus called the Q-Bus; it differed from the Unibus primarily in that addresses and data were multiplexed onto a shared set of wires, as opposed to having separate sets of wires, as in the Unibus. It also differed slightly in how it addressed I/O devices and it eventually allowed a 22-bit physical address (whereas the Unibus only allowed an 18-bit physical address) and block-mode operations for significantly improved bandwidth (which the Unibus did not support).

The CPU's microcode includes a debugger that directly communicated to a standard serial RS-232 or current loop terminal. This was useful because the microcode is the part of the irreducible guts of the computer, a critical part of the control unit. If it doesn't work, there is no computer. The debugger provided a way to examine the computer's registers, memory and input and output devices. Thus, if the CPU worked at all, it was possible to examine and correct the computer's internal state. The built-in debugger avoided the expense and inconvenience of a front panel with an array of switches and lights, which was then the typical way to enter digital data into a near-dead computer.

These two innovations meant that most of the time, the computer just worked. If it did not boot from its big disk, it would boot from its floppy. If the hardware worked at all, it talked to you through a terminal in a familiar way.

Later Q-Bus based systems such as the 11/23 series and 11/73,83 series were based upon chip sets designed in house by Digital Equipment Corporation. Of interest, the Q-Bus PDP-11/83 and Unibus PDP-11/84 shared the same CPU and memory circuit boards. The PDP-11/84 having a Unibus adapter.

There were significant other innovations in the Q-Bus lineup. A system variant of the PDP-11/03 introduced full system Power On Self Test (POST) and the 11/83 introduced a primitive (by today's standards) anticipatory CPU cache pre-load as well as a high speed private memory interconnect (buss).

On later model Q-Bus based systems (such as the PDP-11/73B), microcode also included a memory map and diagnostic utility, and an array of bootstrap programs with which all DEC disk drives were compatible. (This is not to be confused with bootstrap ROM, a feature found on many PDP-11s, often in form of a separate board, which was mapped into the physical address space).


An early publication of Rodnay Zaks from Sybex was A microprogrammed APL implementation ISBN: 0895880059 which is the complete, total source listing for the microcode for a PDP / LSI-11 processor implementing the APL programming language.

[edit] The decline of the PDP-11

The basic design was extremely good, and was continually updated to use newer technologies. Ultimately, however, the 16-bit architecture proved to be a limitation which could not be overcome by tweaks and add-ons. While some models could support larger physical address spaces using memory mapping hardware, all programs were restricted to a 16-bit virtual address space with only 64K bytes of memory. When inexpensive VLSI memory chips became available in the 1980s, PDP-11 software was not capable of using large amounts of memory easily.

DEC's own successor to the PDP-11, the VAX-11 (for "Virtual Address Extension (to the PDP-11)") addressed all of these issues, but was initially aimed at the high-end time sharing market. The early VAXes contained a PDP-11 compatibility mode, so could be considered PDP-11s by application programmers.

As engineers migrated to architectures that supported a larger address space, 32-bit computing began to be supported on microprocessor chips such as the Motorola 68000 and Intel 80386 processors and their successors; eventually the economics of large-scale production of those chips eliminated any cost advantage for the PDP-11. A line of personal computers based on the PDP-11, the DEC Professional series, failed, along with two other DEC PC offerings.

DEC discontinued the final PDP-11 models in 1997. The PDP-11 design and operating system licenses were finally sold to Mentec, Inc., an Irish producer of LSI-11 based boards for Q-Bus and ISA architecture personal computers.

By the late 1990s, not only DEC but most of the New England computer industry which was built around minicomputers like the PDP-11 also collapsed in the face of UNIX and Windows servers.

[edit] Architectural details

The following information is found in DEC's PDP-11 Processor Handbook (see Gordon Bell's 1969 edition).

[edit] General register addressing modes

(R is a general register, 0 to 7; (R) is the contents of that register.)

0. Register - the value is to or from a register: OPR R ; R contains operand
1. Register deferred - register is used as a memory address to read or write: OPR (R) ; R contains address
2. Autoincrement: OPR (R)+ ; R contains address, then increment (R)
3. Autoincrement deferred: OPR @(R)+ ; R contains address of address, then increment (R) by 2
4. Autodecrement: OPR -(R) ; Decrement (R), R contains address
5. Autodecrement deferred: OPR @-(R) ; Decrement (R) by 2, then R contains address of address
6. Index: OPR X(R) ; (R)+X is address, second word of instruction
7. Index deferred: OPR @X(R) ; (R)+X is address (second word) of address

[edit] Program counter addressing modes

The program counter (PC) can also be used as a general purpose register, providing the following effectively additional addressing modes, using the mechanisms of the addressing modes above:

2. Immediate: OPR #N ; Operand is contained in the instruction
3. Absolute: OPR @#A ; Absolute address is contained in the instruction
6. Relative: OPR A ; PC+2+X is address. PC+2 is updated PC
7. Relative deferred: OPR @A ; PC+2+X is address of address. PC+2 is updated PC

[edit] PDP-11 instruction repertoire

The PDP-11 possessed a powerful instruction repertoire.

[edit] Single Operand instructions

One part of the word specifies the operation, referred to as "opcode" (short for "operation code", the second part provides information for locating the operand.

15 6 5 3 2 0
OP-Code Mode Register
  • CLR (clear)
  • COM (ones complement)
  • INC (increment)
  • DEC (decrement)
  • NEG (twos complement negate)
  • TST (test)
  • ASR (arithmetic shift right)
  • ASL (arithmetic shift left)
  • ROR (rotate right)
  • ROL (rotate left)
  • SWAB (swap bytes)
  • ADC (add carry)
  • SBC (subtract carry)
  • SXT (sign extend)

[edit] Double Operand instructions

the first part of the word specifies the operation to be performed, the remaining two parts provide information for locating the operands.

15 12 11 9 8 6 5 3 2 0
OP-Code Mode Register Mode Register
  • MOV (move)
  • ADD
  • SUB (subtract)
  • BIT (bit test)
  • BIC (bit clear)
  • BIS (bit set)
  • XOR (exclusive OR)

[edit] Program Control instructions

The first part of the word specifies the operation to be performed, the second part indicates where the action is to take place in the program.

15 8 7 0
OP-Code Offset
  • BR (branch unconditionally)
  • BNE (branch if not zero)
  • BEQ (branch if zero)
  • BPL (branch if plus)
  • BMI (branch if minus)
  • BVC (branch if overflow clear)
  • BVS (branch if overflow set)
  • BCC (branch if carry clear)
  • BCS (branch if carry set)
  • BLE (branch if <= 0)
  • BGE (branch if >= 0)
  • BLT (branch if < 0)
  • BGT (branch if > 0) (signed compares)
  • BLO (branch if lower)
  • BHI (branch if higher)
  • BLOS (branch if lower or same)
  • BHIS (branch if higher or same) (unsigned compares).
  • SOB (subtract one from register and branch if not = 0).

[edit] Jump & Subroutine instructions

  • JMP (jump)
  • JSR (jump to subroutine)
  • RTS (return from subroutine)
  • EMT (emulator trap)
  • TRAP, BPT (breakpoint trap)
  • IOT (input/output trap)
  • RTI & RTT (return from interrupt).

[edit] Miscellaneous instructions

  • HALT, WAIT (wait for interrupt)
  • RESET (reset UNIBUS)
  • MTPD (move to previous data space)
  • MTPI (move to previous instruction space)
  • MFPD (move from previous data space)
  • MFPI (move from previous instruction space)
  • MTPS (move to processor status word)
  • MFPS (move byte from processor status word).

[edit] Condition Code operations

  • CLC, CLV, CLZ, CLN, CCC (clear relevant condition code)
  • SEC, SEV, SEZ, SEN, SCC (set relevant condition code).

The four condition codes in the processor status word (PSW) are

  • N indicating a negative value
  • Z indicating a zero condition
  • V indicating an overflow condition, and
  • C indicating a carry condition.

[edit] "Extended Instruction Set" (EIS)

The EIS was an option for 11/35/40 and 11/03, and was standard on newer processors.

  • MUL, DIV multiply and divide integer operand to register pair
  • ASH, ASHC arithmetic - shift a register or a register pair. For a positive number it will shift left, and right for a negative one.

[edit] "Floating Instruction Set" (FIS)

The FIS instruction set was an option for the PDP-11/35/40 and 11/03

  • FADD, FSUB, FMUL, FDIV only for single-precision operating on stack addressed by register operand

[edit] "Floating Point Processor" (FPP)

This was the optional floating point processor option for 11/45 and most subsequent models.

  • full floating point operations on single- or double-precision operands, selected by single/double bit in Floating Point Status Register
  • single-precision floating point data format predecessor of IEEE 754 format: sign bit, 8-bit exponent, 23-bit mantissa with hidden bit 24

[edit] "Commercial Instruction Set" (CIS)

The CIS microcode option for 11/23/24, add-in modules for the 11/44, and one version of the 11/74.

  • Various string and decimal instructions used to support COBOL and Dibol.

[edit] Assembly language programming example

Punched tape used for PDP-11
Punched tape used for PDP-11

A complete "Hello, world!" program in PDP-11 macro assembler, to run under RT-11:

        .TITLE  HELLO WORLD
        .MCALL  .TTYOUT,.EXIT
HELLO:: MOV     #MSG,R1 ;STARTING ADDRESS OF STRING
1$:     MOVB    (R1)+,R0 ;FETCH NEXT CHARACTER
        BEQ     DONE    ;IF ZERO, EXIT LOOP
        .TTYOUT         ;OTHERWISE PRINT IT
        BR      1$      ;REPEAT LOOP
DONE:   .EXIT

MSG:    .ASCIZ /Hello, world!/
        .END    HELLO

If this file is HELLO.MAC, the RT-11 commands to assemble, link and run (with console output shown) are as follows:

.MACRO HELLO
ERRORS DETECTED:  0

.LINK HELLO

.R HELLO
Hello, world!
.

(The RT-11 command prompt is ".")

For a more complicated example of MACRO-11 code, two examples chosen at random are Kevin Murrell's KPUN.MAC, or Farba Research's JULIAN routine. More extensive libraries of PDP-11 code can be found in the Metalab freeware and Trailing Edge archives.

[edit] PDP-11 models

The PDP-11 processors tended to fall into several natural groups depending on the original design upon which they are based and which I/O bus they used. Within each group, most models were offered in two versions, one intended for OEMs and one intended for end-users.

[edit] Unibus models

The following models used the Unibus as their principal bus:

  • PDP-11 (later renamed the PDP-11/20) and PDP-11/15 — The original, non-microprogrammed processor; designed by Jim O'Loughlin.
  • PDP-11/35 and 11/40 — A microprogrammed successor to the /20; the design team was led by Jim O'Loughlin.
  • PDP-11/45, 11/50, and 11/55 — A much faster microprogrammed processor that could use semiconductor memory as well as or in addition to core memory.
  • PDP-11/70 — The 11/45 architecture expanded to allow 4 MiB of physical memory segregated onto a private memory bus, 2 KiB of cache memory, and much faster I/O devices connected via the Massbus.
  • PDP-11/05 and 11/10 — A cost-reduced successor to the 11/20.
  • PDP-11/34 and 11/04 — Cost-reduced follow-on products to the 11/35 and 11/05. The PDP-11/09 and 11/39 model names were documented internally to DEC but never produced for sale. The PDP-11/34 concept was created by Bob Armstrong.
  • PDP-11/44 — An extension of the 11/34 that included the cache memory and floating point units as a standard feature. This machine also included a sophisticated serial console and support for 4 MiB of physical memory. The design team was managed by John Sofio.
  • PDP-11/60 — A PDP-11 with user-writable microcontrol store; this was designed by another team led by Jim O'Loughlin.
  • PDP-11/24 — First VLSI PDP-11 for Unibus, using the "Fonz-11" (F11) chip set
  • PDP-11/84 — Using the VLSI "Jaws-11" (J11) chip set
  • PDP-11/94 — J11-based, faster than 11/84

[edit] Q-bus models

The following models used the Q-Bus as their principal bus:

  • PDP-11/03 (also known as the LSI-11/03) — The first LSI PDP-11, this system used a chipset from Western Digital.
  • PDP-11/23 — 2nd generation of LSI (F-11), early units only supported 248 KiB memory, but could be modified for 4 MiB support
  • PDP-11/23+/MicroPDP-11/23 — Improved 11/23 with more functions on processor card (physically a quad-size card rather than dual)
  • MicroPDP-11/73 — The third generation LSI PDP, this system used the "Jaws-11" (J-11) chip set.
  • MicroPDP-11/53 — slower 11/73 with on-board memory
  • MicroPDP-11/83 — faster 11/73 with PMI (private memory interconnect)
  • MicroPDP-11/93 — faster 11/83; final DEC Q-Bus PDP-11 model.
  • Mentec M100 — Mentec redesign of the 11/93, with J-11 chipset at 19.66 MHz, 4 onboard serial ports, 1-4 MiB on-board memory, and optional FPU.
  • Mentec M11 — processor upgrade board; last microcode implementation of PDP-11 instruction set by Mentec, using the TI 8832 ALU and TI 8818 microsequencer from Texas Instruments
  • Quickware QED-993 — high performance PDP-11/93 processor upgrade board

[edit] Models without standard bus

  • PDT-11/110
  • PDT-11/130
  • PDT-11/150

The PDT series were desktop systems marketed as "smart terminals". The /110 and /130 were housed in a VT100 terminal enclosure.

  • PRO-325
  • PRO-350
  • PRO-380

The DEC Professional series were desktop PCs intended to compete with IBM's earlier 8088 and 80286 based personal computers. The models were equipped with 5 1/4" floppy disk drives and hard disks, except the 325 which had no hard disk. The CPUs were from the LSI-11 line running P/OS, which was essentially RSX-11M+ with a menu system on top. As the design was intended to avoid software exchange with existing PDP-11 models, their ill fate in the market was no surprise for anyone except DEC.

[edit] Models that were planned but never introduced

  • PDP-11/27 — A Jaws-11 implementation that would have used the VAXBI Bus as its principal I/O bus.
  • PDP-11/68 — A follow-on to the PDP-11/60 that would have supported 4 MiB of physical memory.
  • PDP-11/74 — A PDP-11/70 that was extended to contain multiprocessing features. Up to four processors could be interconnected, although the physical cable management became unwieldy. Another variation on the 11/74 contained both the multiprocessing features and the Commercial Instruction Set. A substantial number of prototype 11/74's (of various types) were built and at least two multiprocessor systems were sent to customers for beta testing, but no systems were ever officially sold. A four processor system was maintained by the RSX-11 operating system development team for testing and a uniprocessor system served PDP-11 engineering for general purpose timesharing. The 11/74 was due to be introduced around the same time as the announcement of the new 32 bit product line and the first model - the VAX 11/780. Rumour/Legend or conspiracy theory held that the reason the 11/74 was cancelled was due to its higher performance compared to the 11/780 (see, for example [2]). Marketing was therefore concerned that the availability of a higher performing PDP-11 would slow migration to the new VAX. This was not the case. Rather, the ability to maintain the product in the field was the issue. However conspiracy or not, DEC was never able to successfully migrate its entire PDP-11 customer base to the VAX. The primary reason was not performance, but the PDP-11's superior real-time responsiveness.

[edit] Special purpose versions

DEC GT40 running Lunar Lander
DEC GT40 running Lunar Lander
  • GT40 — Vector graphic terminal built from a PDP-11/05
  • GT42 — Vector graphic terminal built from a PDP-11/10
  • GT44 — Vector graphic terminal built from a PDP-11/40
  • H-11 — Heathkit OEM version of the LSI-11/03
  • VT103 — VT100 with backplane to host a LSI-11
  • VT173 — A high-end typseset terminal containing an 11/03
  • MINC-11 — Laboratory system based on 11/03 or 11/23
  • C.mmp — Multiprocessor system from Carnegie Mellon University

[edit] Clandestine clones

The PDP-11 was sufficiently popular that several unauthorized clones were produced behind the Iron curtain. At least some of these were pin-compatible with DEC's PDP-11s and could share peripherals and system software. These include:

[edit] Operating systems

Several operating systems were available for the PDP-11

From Digital:

From third parties:

[edit] PDP-11s still in service

The computer system in the METROL metropolitan train control centre in Melbourne, Australia is still in regular commercial service[citation needed]. This system runs an operating system coded in Swedish PASCAL for the creation of train timetables, fleet management and passenger information displays. Several nuclear plants around the world, including Canada, the Netherlands and Sweden, still run PDP-11s.[citation needed] Many research institutions still regularly run PDP-11s for data collection or instrumentation control. Australia Post still use PDP-11/93's running RSX-11 on some of their older Optical Character Recognition machinery. Flight simulators (such as the 747 operated by MK Airlines) use a PDP-11.

[edit] See also

[edit] External links

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