Parallel Random Access Machine

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A Parallel Random Access Machine (PRAM) is an abstract machine for designing the algorithms applicable to parallel computers. It eliminates the focus on miscellaneous issues such as synchronization and communication, but lets designer think explicitly about the exploitation of concurrency. In terms of Flynn's taxonomy, PRAMs are multiple instruction multiple data (MIMD) computers.

The operation of a synchronous PRAM can result in simultaneous access by multiple processors to the same location in shared memory. There are several variants of our PRAM model, depending on whether such simultaneous access is permitted or prohibited. As accesses can be reads or writes, there are four possibilities:

  1. Exclusive Read Exclusive Write (EREW) - every memory cell can be read or written to by only one processor at a time
  2. Concurrent Read Exclusive Write (CREW) - multiple processors can read a memory cell but only one can write at a time
  3. Exclusive Read Concurrent Write (ERCW) - never considered
  4. Concurrent Read Concurrent Write (CRCW) - multiple processors can read and write
Common CRCW - if processors writing the same value, OK; otherwise, it is an illegal operation
Arbitrary CRCW - one attempt is successful (we don't know which in advance), others retire
Priority CRCW - rank indicates who gets to write

Algorithms are written in pseudo-code as there is no actual implementation of a PRAM. However, these kinds of algorithms are useful for understanding the exploitation of concurrency, dividing the original problem into similar sub-problems and solving them in parallel.

[edit] See also

[edit] References

Keller, Jörg; Christoph Keßler, Jesper Träff (2001). Practical PRAM Programming. John Wiley and Sons. 0471353515. 

Topics in Parallel Computing  v  d  e 
General High-performance computing
Parallelism Data parallelismTask parallelism
Theory SpeedupAmdahl's lawFlynn's TaxonomyCost efficiencyGustafson's LawKarp-Flatt Metric
Elements ProcessThreadFiberParallel Random Access Machine
Coordination MultiprocessingMultitaskingMemory coherencyCache coherencyBarrierSynchronizationDistributed computingGrid computing
Programming Programming modelImplicit parallelismExplicit parallelism
Hardware Computer clusterBeowulfSymmetric multiprocessingNon-Uniform Memory AccessCache only memory architectureAsymmetric multiprocessingSimultaneous multithreadingShared memoryDistributed memoryMassively parallel processingSuperscalar processingVector processingSupercomputer
Software Distributed shared memoryApplication checkpointing
APIs PthreadsOpenMPMessage Passing Interface (MPI)
Problems Embarrassingly parallelGrand Challenge


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