Panasonic M2

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This article discusses the M2 game console. For information about the video tape format please see Panasonic MII

The Panasonic M2 was a video game console design developed by 3DO and then sold to Matsushita (known internationally as Panasonic) for $100,000,000 [1]. Before it could be released, however, Matsushita cancelled the project in late 1997, unwilling to compete against fellow Japanese electronics giant Sony's PlayStation due to the failure of their own 3DO Interactive Multiplayer console. The M2 was cancelled so close to release, marketing had already taken place in the form of flyers, and one of its prospected launch titles, WARP's D2, had several gameplay screens in circulation (this game was later redesigned from scratch to be released on the Sega Dreamcast).

Development kits and prototypes of the machine are very valuable pieces among today's collectors. M2's technology lived on at Matsushita; integrated in the multimedia players FZ-21S and FZ-35S, both released in 1998. Both products were aimed at professionals working in medicine, architecture and sales, not home users.

Yet the M2 did see some use as a game machine - namely, a short-lived arcade board by Konami. [2] As games ran straight from the CD-ROM drive, it suffered from long load times and a high failure rate, so only five games were developed for it.

[edit] Technical specifications

Central Processing Unit - Twin PowerPC 602 CPUs at 66 MHz.
- 32-bit RISC microarchitecture
- PowerPC CPU designed for consumer electronics applications. The only scalar PowerPC
- 1.2 watts power usage each
- 32-bit general purpose registers and integer ALUs, 64-bit data bus at 33 MHz
- 4 KiB data and instruction caches (Level 1). No Level 2 cache
- 1 integer unit, 1 floating point unit, no branch processing unit, 1 load/store unit
- SPECint92 rating of 40 each, approximately 70 MIPS each.
- 1 million transistors manufactured on a 0.50 micrometre CMOS process
Custom ASICs
- BDA:
  - Memory control, system control, and video/graphic control
  - Full triangle renderer including setup engine, MPEG-1 decoder hardware, DSP for audio and various kinds of DMA control and port access
  - Random access of frame buffer and z-buffer (actually w-buffer) possible at the same time
- CDE:
  - Power bus connected to BDA and the two CPUs
  - "bio-bus" used as a low-speed bus for peripheral hardware
Renderer capabilities:
- 1 million textured triangles/s geometry rate
- 100 million pixels/s fill rate
- shading: flat shading and gouraud shading
- texture mapping
- decal, modulation blending, tiling (16K/128K texture buffer built-in)
- hardware z-buffer (16-bit) (actually a block floating point with multiple (4) range w-buffer)
- object-based full-scene anti-aliasing
- alpha channel (4-bit or 7-bit)
- 320x240 to 640x480 resolution at 24-bit color
Sound hardware - 16-bit DSP at 66 MHz (within BDA chip)
Media - Quad-speed CD-ROM drive (600 KB/s)
RAM - Unified memory subsystem with 8 MB/s
- 64-bit bus resulting in peak 533 MB/s bandwidth
- Average access 400 MB/s
Full Motion Video - MPEG-1
Writable Storage - Memory cards from 128 KiB to 32 MiB
Expansion Capabilities - 1 PCMCIA port (potentially used for Modems, Ethernet NICs, etc)