Multi-threshold CMOS

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Multi-CMOS (MTCMOS) utilized transistors with multiple threshold voltages (Vt) to optimize delay or power. Lower Vt devices are used on critical delay paths to minimize clock periods. Higher Vt devices are used on non-critical paths to reduce static leakage power without incurring a delay penalty. Typical high Vt devices reduce static leakage by 10x compared with low Vt devices. One method of creating devices with multiple threshold voltages is to apply different bias voltages (Vb) to the base or bulk terminal of transistors. In NMOS devices, lower Vb will increase Vt, increase delay, and reduce static leakage.

A common MTCMOS approach for reducing power uses sleep transistors. Logic is supplied by a virtual power rail. Low Vt devices are used in the logic for speed. The logic may be turned off by collapsing the virtual power rail. High Vt devices connecting the power rails and virtual power rails are turned off in sleep mode. High Vt devices are used as sleep transistors to reduce static leakage.