MPC5xx
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The MPC5xx family of processors such as the MPC555 and MPC565 are 32-bit PowerPC embedded microprocessors that operate between 40 and 66 MHz and are frequently used in automotive applications including as engine and transmission controllers. They are generally considered microcontrollers because of their integrated peripheral set and their unusual architecture: no MMU, large on-chip SRAM and very large (as much as 1 mebibyte) low latency access on-chip flash memories, which means their architecture is tailored to control applications. Instead of a block-address translation and a hardware-driven, fixed-page address translation prescribed by the first PowerPC specification, the 5xx cores provided a software-driven translation mechanism that supported variable page sizes. This model is the basis for the embedded MMU model in the current Power ISA v.203 specification.
MPC5xx – All PowerPC 5xx family processors share this common naming scheme.
The development of the PowerPC 5xx family is discontinued in favour for the more flexible and powerful PowerPC 55xx family.
[edit] Characteristics
The peripherals on each model vary, but frequently include analog-to-digital converters (QADC), Time Processor Units (TPU), GPIO, and UARTS/serial (QSMCM). The MPC5xx family descends from the MPC8xx PowerQUICC family core, which means it uses a Harvard architecture, single issue core. Unlike the 8xx family, the 5xx variants have a floating point unit. While some of the earlier chips like the MPC509 had an instruction cache, the recent chips have the capability to contain large amounts of NOR flash memory on-board which is capable of bursting instructions to the processor. Some low-cost chips omit the flash memory because it adds a lot of die area, driving up the price of the chip. Many controller applications run very long control loops where there is not a large dataset and low latency, deterministic access to both data and instruction routines is more important. If most of the data can be stored in the on-chip SRAM available to the datapath of the processor in a single cycle, performance can be quite good. If data must be accessed off-chip frequently, performance can be reduced because the chip cannot burst data accesses from external RAM and has a very slow bus access protocol. Because of the simple memory interface that can be programmed by setting a default memory location and writing a few base registers, the chips are quite popular with hobbyists as well as with automotive and industrial developers.
