Montvale (processor)

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This article contains information about a scheduled or expected future product. It may contain preliminary or speculative information, and may not reflect the final version of the product.

Montvale is the code-name of a future release of Intel's Itanium Processor Family (IPF). Like other Itanium processors, it will implement the IA-64 instruction set architecture. It is not yet known what the official marketing name for the product will be.

Current estimates suggest that Montvale will be released approximately one year after Montecito, or approximately during the fourth quarter of 2007.

In contrast to earlier speculations, Montvale will not shrink the die size to 65nm. Earlier data suggested that Montvale's clock speed would have likely hit 2.5-2.6 GHz, using a 400 MHz FSB. More recently, people speculate that the processor may not reach default clock speeds in excess of 2.0 GHz^{[citation needed]}.

It is also very likely that Montvale, like Montecito before it, will bring an update of compiler technology, leading to a significant improvement in the performance characteristics of the Itanium Processor Family.

[edit] Foxton power management

The original design called for a highly advanced clock generation and distribution network. Foxton continuously measures total power draw, processor loads, voltage, clock distribution quality across the entire device, and able to produce extremely fine voltage-to-clock granularity under dynamic conditions. As a result, Foxton enables a chip to overcome the power overhead of factory adjusted voltage-to-frequency settings, which by necessity carry a significant margin of extra to ensure stability against voltage variances. This overhead means lot higher power consumption, since the correlation between operating voltage and power consumption is on the square. Foxton gives power efficiency any given clock rate, on the first hand, but it is not the reason Intel gave it birth. Itanium 2 processors implements a wide core, which has an enormous computing capability, however, there are a lot of codes which does not utilize all the resources. Lower utilization means lower transistor switching activity, which leads to lower power consumption. Today's MPUs are limited by power, thus consumption below maximal specifications results in waste of performance. Because Itanium 2 maintains a wide and capable architecture, the power difference between the highest activity and average codes is quite a gap that could be filled by increasing processor clock rate. This is the main purpose of Foxton technology.

A Foxton-enabled chip has a variable frequency adjusted to a nominal power envelope. Clock and voltage are adjusted to keep the chip's consumption within the envelope. Depending on the actual usage pattern the chip will be able to scale up or down, feeding the core with proper voltage. Under so called low activity workloads which generate less heat while being executed Montvale speeds up till it reaches the target power, and inversely, extreme activity loads may cause the chip to reduce clock rate and core voltage. Additionally, the nominal power envelope can be adjusted from software. Low-activity workloads are rather integer-intensive computations, mostly commercial, database applications. They should be boosted by around a factor of 10% compared to a "fixed clock" scenario. High activity workloads are rather floating point-intensive computations, like scientific and R&D simulations. Nominal clock speeds of chips might be based on power drained by these intensive computations. It was said earlier that Foxton's clock scaling can be disabled if required.

Foxton will likely arrive in 2007. This delay may be a result of the validation process of such a highly complex high-end MPU.

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