Talk:MIPS architecture

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Contents 1 MIPS syscalls? 2 Major designers and contributors 3 Influence on SPARC 4 Microprocessor support in R3000 5 Use in TiVo 6 MDMX not clear 7 Sort of biased, but… 8 Instruction Set Summary 9 Influence on later RISC ISAs 10 Trivia 11 VPEs, TCs, ... 12 Opcode format unclear 13 Processor speeds 14 Mipsel 15 Free MIPS64 Simulator

[edit] MIPS syscalls?

You speak about MIPS syscall... But are you sure they aren't SPIM syscall? Has the processor predefined syscalls???

I'm not sure what your question is. SYSCALL is an instruction implemented by the hardware. It would be used by the Operating System with different hint codes to call the relevant system call software. Since SPIM is a software emulator/simulator of the hw architecture, it would/should implement this instruction. Dyl 17:29, 28 September 2006 (UTC)

I'm speaking about the table entitled "MIPS system calls". It seems strange to me that MIPS has fixed system calls for print_int (1) or print_string (4).

Ah, sorry about my misunderstanding. MIPS didn't fix the system calls. These values are probably what's used by some OS kernel implemented on MIPS CPUs. That emulator just chose to copy what a particular OS does. If you implement both the kernel and the compilers/assemblers, you can pick your own values. Dyl 15:58, 30 September 2006 (UTC)

So may be we should rename the table. Something like "examples of MIPS system calls" or remove it ...

[edit] Major designers and contributors

It would be nice to list some major designers and contributors.

I have imperfect knowledge about this. Craig Hansen was the initial architect. Ed Hudson, John Moussouris, Tom Riordan, Chris Rowen, and Dan Freitas are often listed as some of the main implementors in the early days. Dyl 17:29, 28 September 2006 (UTC)

[edit] Influence on SPARC

I'd like to question the influence on SPARC. There were three RISC designs very early, that were demonstrations of the technology.

1. The IBM effort under John Cocke. This was virtually unknown outside IBM until much, much later, but may have been the inspiration for IBM projects including ROMP, Power, and PowerPC.
2. The Berkeley RISC project. An academic project that was probably the main inspiration for SPARC.
3. The Stanford project. An academic project that was definitely the main inspiration for the commercial MIPS RISC.

SPARC and (commercial) MIPS were developed at much the same time so it is unlikely that commercial MIPS had much influence on SPARC. The original Stanford chip was a bit older than SPARC, and the SPARC people were certainly aware of it, but in looking at the major differences between Stanford and Berkeley RISC (sliding register window only in Berkeley, and not much else) SPARC follows the Berkeley model.

Marice Wilkes states (in the foreword to Patterson/Hennessy) that MIPS is more-or-less the Stanford RISC project while SPARC is the commercialised Berkeley RISC. I therefore reformulated the sentence so that both are credited with influencing later RISCs. --Robbe

[edit] Microprocessor support in R3000

The microprocessor support in the R3000 may have been flawed (I don't really know), but it was NOT generally unused. SGI produced a very popular range of high performance graphics workstations featuring multiple R3000s (the 4D 2x0, 4D/3x0 and 4D/4x0 series) and SGI was far and away MIPS' largest buyer at that point (1990-1993). I also know that Ardent produced a four processor R3000 machine (the Ardent Titan 3000). I am loathe to admit it but DEC did too. The 58x0 series was shameful—DEC didn't really have a fast enough bus for four R3000s, let alone two, so the machines literally got slower as you added more CPUs. Not to mention that the whole thing relied on a VAX processor for the ROM.

Surely you mean 'multiprocessor'? However, I would like to know some more about this, does anyone have any external links where the supposed flaws are explained? Pipatron 10:17, 30 November 2006 (UTC)

[edit] Use in TiVo

I believe the Series II TiVo's use MIPS and that's likely a high enough profile use to warrant a mention.

[edit] MDMX not clear

If MDMX is an integer SIMD instruction set why does it use 64-bit floating point registers ? Please make it clear in the text. --Hdante 9 July 2005 06:16 (UTC)

The idea was that if you were dealing with digital media code, it's unlikely you would be doing floating-point at the same time. MDMX was a cheap way of adding media operations without changing the compilers much (adding a new register set). In the long run, this wasn't too popular nor aggressive enough. Dyl 17:29, 28 September 2006 (UTC)

[edit] Sort of biased, but…

The article tends to be pretty pro-MIPS without putting it in the context of what other chips have been its contemporaries; for instance, it doesn't mention the ARM architecture at all - and I'd be more than a little surprised to hear that the two arches didn't have comparable numbers of devices out there. (I suspect that there's more ARMs, actually.)

There's also the inconsistently-applied moniker MIPS itself; for instance, while the Sony Playstation does have an actual MIPS Technololgies CPU, the PS2's core has an R5900 made by Toshiba. I think it might be a good idea to separately delineate the mips model (e.g. the R1000) from the mips architecture (e.g. MIPS32.) --moof 12:51, 26 March 2006 (UTC)

I think the level of boosterism is at the same level on the ARM article. That article doesn't mention other architecture neither. eg. A little architecture from Intel/AMD or low-end microcontrollers . Besides, neither article is trying to quantify the volume leaders (which ARM would currently win). Dyl 02:36, 7 April 2006 (UTC)

I wrote a substantial portion of the article, and did so basically in isolation of articles on the other designs noted above. This was really a function of the way I wrote the article; I simply gathered references about the topic, and wrote.

I can understand, in retrospect, why this would end up with a somewhat myopic view. I hope I don't go too far by suggesting that if you had access to information on only one thing, anything from apples to chipsets, it's likely that any article created from those sources alone would likely end up that way.

So, I'd be happy to hear from a few other people too, is this article too tightly focused on MIPS, to the point where it seems like boosterism? And it's not the first time someone has mentioned this about an article I was prime on, which is the basis for my concern. Maury 21:16, 9 June 2006 (UTC)

[edit] Instruction Set Summary

The article uses the non-standard term of CONST, while all MIPS official documentation uses the term IMMEDIATE. Using the official term would be better IMHO. Dyl 15:37, 2 May 2006 (UTC)

[edit] Influence on later RISC ISAs

I've just WP:BOLDly changed the last sentence of the Lede section from

The design of the MIPS CPU family, together with SPARC, another early RISC architecture, greatly influenced later RISC designs like DEC Alpha.

to:

The design of the MIPS CPU family greatly influenced later RISC architectures such as DEC Alpha.

Why? Our DEC Alpha article says (quite rightly, I believe) that the Alpha was indeed greatly influenced by MIPS, but does not mention SPARC. I'd guess that the Power Architecture was influenced by MIPS to at least some extent, but not much by SPARC. The only later architecture which could be regarded as showing much SPARC influence is IA-64, and there's a good case that IA-64 is not a RISC architecture; my "such as DEC Alpha" wording is intended to avoid that issue.

This is a lot of fuss over a small issue, but I've done it anyway. Cheers, CWC(talk) 08:28, 29 September 2006 (UTC)

[edit] Trivia

Regarding the recent edit to the Trivia section, I'm of the opinion that the piece of information doesn't belong here; rather, it belongs with the information for the Mips character, which can be found at Super Mario 64; the note about the connection between Mips the rabbit and MIPS the processor architecture is found there. Wikipedia:Trivia indicates it would be more appropriate there, too. This is why I removed the section a second time. – Mipadi 12:26, 18 October 2006 (UTC)

[edit] VPEs, TCs, ...

[1] DDJ article, "Multi-core Performance In Single-Core Using Multi-threaded Virtual Multiprocessors" -- Robocoder (t|c) 19:04, 10 December 2006 (UTC)

[edit] Opcode format unclear

There's a table with the opcode format and register numbers "rt", "rs" and "rd", but there is no explanation what these registers actually are. I suspect that "rt" is the target register of an instruction, "rs" is the source and "rd" an additional data register. —The preceding unsigned comment was added by 131.234.158.246 (talk) 13:25, 20 February 2007 (UTC).

It's pretty unclear in the MIPS manual too. They're supposedly "source", "destination" and "target". rt can behave as a source or destination depending on the instruction. Unfortunately there's a few instructions which just do whatever they feel like - like mfc0, which reads from rd and writes to rt. I think it's best to treat them as arbitrary labels. Asuffield 14:43, 20 February 2007 (UTC)

[edit] Processor speeds

For the "MIPS microprocessor specifications" table, there is a note that differences in the amount of secondary cache can change (and certainly, 2Mb R12000s and 4Mb R14000s were common SGI configurations (on the Octane and Fuel respectively)) but also note that there were 900MHz R16000 Fuel and 4x1GHz R16000 Tezro variations - so 800MHz is certainly not the limit here!

87.112.6.190 19:36, 8 March 2007 (UTC)

[edit] Mipsel

Please add a definition for mipsel

NigelHorne 16:46, 30 March 2007 (UTC)

[edit] Free MIPS64 Simulator

Hello! I belong to a free (as in free speech) MIPS64 CPU Simulator development team. Do you think that it's acceptable to add the simulator's URL to the "External links" sections? The URL is http://www.edumips.org, the simulator's name is EduMIPS64. Thanks!