Meiko Scientific

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Meiko Scientific Ltd. was a British supercomputer company based in Bristol, founded by members of the design team working on the INMOS transputer microprocessor. When, in late 1985, INMOS management suggested the release of the transputer be delayed, Miles Chesney, David Alden, Eric Barton, Roy Bottomley, James Cownie and Gerry Talbot resigned and formed Meiko (Japanese for "well-engineered") to start work on massively parallel machines based on the processor. Nine weeks later they demonstrated a transputer system based on experimental 16 bit Transputers at the SIGGRAPH in San Francisco in July 1985. In 1986 a system based on 32 bit T414 transputers was launched as the Meiko Computing Surface. By 1990, Meiko had sold more than 300 systems and grown to 125 employees.

The original Computing Surface was based on T414 transputers connected through a hand-pluggable set of links. Meiko-designed link switch chips were soon introduced to allow the connection topology to be more dynamic. The T414s were later replaced with the more capable T800 transputer as these became available from 1987 onwards. The Computing Surface could run either Meiko's version of the INMOS Transputer Development System or a Unix-like operating system called MeikOS.

In 1988, Meiko launched the In-Sun Computing Surface system, which repackaged the Computing Surface into VME boards suitable for installation in Sun-3 or Sun-4 systems. The Sun acted as a "front end" host system for managing the transputers, running development tools and providing mass storage.

Meiko later integrated SPARC and Intel i860 processors into the Computing Surface architecture. The introduction of SPARC allowed the popular SunOS operating system to be integrated into Computing Surface systems similarly to the In-Sun Computing Surface. i860 processors were used for their much greater floating-point performance compared to transputers.

A major drawback of the Computing Surface architecture was poor I/O bandwidth for general data shuffling. Although aggregate bandwidth for special case data shuffling could be very high, the general case has very poor performance relative to the compute bandwidth. This made the Meiko Computing Surface uneconomic for many applications.

In 1993, Meiko launched their second-generation CS-2 system. This was an all-new scalable modular architecture based around SPARC and Fujitsu vector processors, running Solaris, connected by a high-performance multi-stage packet-switched interconnect implemented in custom silicon.

The network was implemented in a NIC (known as Elan) and a cross-bar switch (known as Elite). The Elite switches were used to create a full "fat-tree" interconnect, which provided scalable bi-sectional bandwidth. The Elite could also support broadcast to a contiguous set of nodes, and collect and coombine a response, allowing efficient implementation of broadcast and barriers. The Elan contained a processor which implemented a cut-down version of the SPARC instruction set and included page tables and dynamic address translation, allowing protocol code to be offloaded from the node CPU. By also providing multiple sets of control registers this allowed complete virtualization of the NIC, and thus direct transfer of data from user-space in a process on one processor to user-space in a process on another processor while maintaining security and without requiring operating system intervention. The fundamental communciation primitive implemented by the Elan was remote direct memory access. Message passing systems were built on top of this primitive.

Meiko ran into financial difficulties in the mid-1990s and the Meiko technical team and technology was transferred to a joint venture company called Quadrics Supercomputers World Ltd. (QSW), formed by Alenia Spazio of Italy in mid-1996. At Quadrics, the CS-2 interconnect technology was developed into QsNet. As of mid 2006, a Meiko website is up, though limited to customers.

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[edit] References

  • Arthur Trew and Greg Wilson (eds.) (1991). Past, Present, Parallel: A Survey of Available Parallel Computing Systems. New York: Springer-Verlag. ISBN 0-387-19664-1.