Low Pin Count

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Low Pin Count interface IT8705F. Involved in fan speed control, floppy and keyboard management, smart card reader, MIDI interface and many other tasks (described in [1]).

The Low Pin Count bus, or LPC bus, is used on IBM-compatible personal computers to connect low-bandwidth devices to the CPU, such as the boot ROM and the "legacy" I/O devices (behind a super I/O chip). The "legacy" I/O devices usually include serial and parallel ports, keyboard, mouse, floppy disk controller and - more recently - the Trusted Platform Module. The physical wires of the LPC bus usually connect to the southbridge chip on a PC motherboard.

The LPC bus was introduced by Intel in 1998 as a substitute for the Industry Standard Architecture (ISA) bus. It resembles ISA to software, although physically it is quite different.

The LPC specification defines seven mandatory signals required for bidirectional data transfer. Four of these signals carry the multiplexed address and data. The other three are control signals (frame, reset and clock).

The six optional signals defined in the specification can be used for interrupt support, direct memory access, waking the system from a low power ("sleeping") state and notifying the LPC peripherals that power will soon be removed.

LPC I/O read transfer rate, at 33.3MHz, is 16.67Mbytes/sec.

LPC's main advantage is that it requires only seven signals, and is therefore easy to route on modern motherboards, which are often quite crowded. An integrated circuit using LPC will need 30 to 72 fewer pins than its ISA equivalent. Also, LPC is intended to be a motherboard-only bus. No connector is defined, and no LPC peripheral daughterboards are available.

The LPC specification was authored by Intel.