Latch (electronics)
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In electronics, a latch is a data storage device used to store information in sequential logic systems. One latch can store one bit of information. In most cases, a latch can also be called a flip-flop; in some cases, especially in synchronous edge-triggered circuits, flip-flops may be distinguished from latches.
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[edit] Simple set-reset latches
[edit] SR latch
The most fundamental latch is the simple SR latch (or simple SR flip-flop), where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (negative OR) logic gates. The stored bit is present on the output marked Q.
Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R is held low, then the Q output is forced high, and stays high when S returns low; similarly, if R (Reset) is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns low.
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The R = S = 1 combination is called a restricted combination because, as both NOR gates then output zeros, it breaks the logical equation Q = not Q. The combination is also inappropriate in circuits where both inputs may go low simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or 0 depending on the propagation time relations between the gates (a race condition). In certain implementations, it could also lead to longer ringings (damped oscillations) before the output settles, and thereby result in undetermined values (errors) in high-frequency digital circuits. This condition is therefore sometimes avoided.
To overcome the restricted combination, one can add gates to the inputs that would convert (S,R) = (1,1) to one of non-restricted combinations. That can be:
- Q = 1 (1,0) — referred to as an S-latch
- Q = 0 (0,1) — referred to as an R-latch
- Keep state (0,0) — referred to as an E-latch
[edit] SR latch
This is a variety of the simple SR latch built with NAND (negative AND) logic gates. Set and reset now becomes active low signals, denoted S and R respectively, operation is otherwise identical to that of the SR latch.*
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* SR-latches have been preferred, despite a notational inconvenience of active-low inputs, as NAND gates are cheaper in the diode-transistor logic (DTL) and transistor-transistor logic (TTL) originally used in standard integrated circuits. Today, even most 7400 series chips are built in CMOS technology, so this has changed.
[edit] Gated latches
[edit] Gated SR latch
A Synchronous SR latch (sometimes clocked SR flip-flop) can be made by adding a second level of NAND gates to the inverted SR latch (or a second level of NOR gates to the direct SR latch). The extra gates further invert the inputs so the simple SR latch becomes a gated SR latch (and a simple SR latch would transform into a gated SR latch with inverted enable).
With E high (enable true), the signals can pass through the input gates to the encapsulated latch; all signal combinations except for (0,0) = hold then immediately reproduce on the (Q,Q) output, i.e. the latch is transparent.*
With E low (enable false) the latch is closed and remains in the state it was left the last time E was high.
The enable input is sometimes a clock signal, but more often a read or write strobe.
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* Note that, with several transparent latches following each other, the signal would propagate through all of them.
[edit] Gated D latch
| A D-type transparent latch | |
| D | Input |
| C | Enable/clock |
| Q | Output |
| Q' | Inverse of Q |
This latch is closely related to the gated SR latch and can be similary constructed. It is also known as transparent latch, data latch, or simply gated latch. It has a data input and an enable signal (sometimes named clock, or control). The word transparent comes from the fact that, when the enable input is on, the signal would propagate directly through the circuit, from the input D to the output Q.
Transparent latches are typically used as I/O ports or in asynchronous systems.* They are available as integrated circuits, usually with multiple latches per circuit. For example, 74HC75 is a quadruple transparent latch in the ubiquitous 7400 series.
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The truth table shows that when the enable/clock input is 0, the D input has no effect on the output. When E/C is high, the output equals D.
* Transparent latches are also sometimes used in synchronous two-phase systems (for reduced transistor count); however, in single-phase synchronous systems with direct feedback, master-slave devices (often edge-triggered) must be used to avoid analog oscillations.
[edit] JK latch
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The JK latch follows the following state table:
| JK latch truth table | ||||
| J | K | Qnext | Comment | |
| 0 | 0 | Qprev | No change | |
| 0 | 1 | 0 | Reset | |
| 1 | 0 | 1 | Set | |
| 1 | 1 | Qprev | Toggle | |
[edit] See also
[edit] References
- Fundamentals of Digital Logic by Brown and Vranesic
- S.P.Vingron: `Switching Theory. Insight through Predicate Logic.' Springer Verlag, 2003. ISBN 3-540-40343-4 — extensively covers the theory of latches
