KARL

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KARL is the acronym of KAiserslautern Register transfer Language a pioneering early hardware description language also comping along with a graphic companion language ABL ("A Blockdiagram Language") and its hierarchical graphic editor ABLED. Both, KARL and ABL have been initiated in the 1970 by Reiner Hartenstein. KARL has been the first hardware description language supporting both, functional and structural description, so that also the structured design of VLSI floor plan layout is supported.

Based on these structural KARL features Reiner Hartenstein has proposed in the early 1980ies the use of Term Rewriting for the Automatic derival of a well structured VLSI layout floorplan from a Mathematical formula used as the problem specification. Two decades later this proposal has been implemented by Mauricio Ayala-Rincon. So far Rewriting methods had been used for verification, i. e. in a bottom-up manner. But by his idea Hartenstein has been the initiator of using Rewriting in a top-down manner for synthesis instead of verification.

Throughout the 1970ies and the 1980ies, before around 1989 VHDL came up, KARL has been the world-wide most successful hardware description language. Throughout the 1980ies, under support by the commission of the European Union the multi-national CVT project and its successor, the multi-national CVS project implemented around the KARL simulator the first complete design framework in the world, including KARL simulator, ABL graphic layout editor (ABLED), PLA generator, standard cell placement and routing, automatic test pattern generation and analysis.

[edit] Literature

R. Hartenstein: Fundamentals of Structured hardware Design - A Design Language Approach at Register Transfer Level; North Holland/American Elsevier Amsterdam/New York 1977
R. Hartenstein: The History of KARL and ABL; in: J. Mermet (editor): Fundamentals and Standards in Hardware Description Languages; ISBN 0-7923-2513-3, Kluwer Academic Publishers, September 1993
A. Bonomo, G. Girardi, A. Lecce, L. Maggiulli: GENMON: a specialized ABL editor for design methodology descriptions; Proc.2nd ABA-KUS workshop, Innsbruck, Austria, Sept. 1988
A. Bonomo, M. Italiano, L. Lavagno, L. Maggiuli, M. Melgara, M. Paolini, I. Stamelos: BACH (Behavioural-Level Automated Compilation of Hardware): An Integrated ASIC Synthesis System; ESPRIT Technical Week, Brussels, Belgium 1988
V. G. Moshnyaga, H. Onodera, K. Tamaru, H. Yasuura: A Language for Designing Data-Path Module Generators; Int’l Design Workshop "Russian Workshop’92", Moscow, Russia
V. G. Moshnyaga, H. Yasuura: A Data-Path Modules Design from Algorithmic Representations; IFIP WG 10.5 Workshop on Synthesis, Generation and Portability of Library Blocks for ASIC Design, Grenoble, France, Mar 1992
V. G. Moshnyaga, H. Yasuura: A Language for Designing Module Generators; Proc. SASIMI’92 - Synthesis and Simulation Meeting and Int’l Exchange, Kobe, Japan, Apr. 1992
M. Ayala-Rincon et al.: Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic; Proceedings of the 17th symposium on Integrated circuits and system design 2004, Pernambuco, Brazil, September 07 - 11, 2004