JHDL
From Wikipedia, the free encyclopedia
JHDL (Just-Another Hardware Description Language) is a low level hardware description language, focused primarily on building circuits via an Object Oriented approach that bundles collections of gates into Java objects. Implemented as a toolset and class library on top of the Java programming language, its primary use is for the design of FPGAs. Particular attention was paid to supporting the Xilinx series of chips.
When the design is ready to be placed in a fabric, the developer simply generates an EDIF netlist and imports it into his favorite toolkit. Once imported, the developer should be able to transfer the circuit via a JTAG cable. EDIF netlisting is supported for the XC4000, Virtex, and Virtex-II series of FPGAs.
JHDL was developed at BYU in the Configurable Computing Laboratory.
[edit] Features
The JHDL language features include:
- Structural hardware design
- Flexible module generators
- Table-generated finite state machines
- A graphical "Workbench" toolkit
Behavioral synthesis is not yet fully supported.
The integrated JHDL Workbench environment is designed to allow developers to graphically test and trace their circuit designs. This tool includes:
- A graphical schematic viewer
- A multiclock cycle-based simulator
- A command line interface
- A complete list of all wires and gates
- A complete status of all values passing through the circuit
[edit] Naming
Originally, the J in "JHDL" stood for "Java". However, to prevent trademark issues, the name has been backronymed to stand for Just-Another Hardware Description Language.
