Talk:Instruction pipeline

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One frustrating aspect of this entry is that it doesn't offer a simple and concrete idea of the principle of piplining right up front. Would the following analogy (or something like it) help, or would it serve as a distraction?

Imagine a laundry room with a washing machine and a dryer. The washer takes 30 minutes to wash, and the dryer takes 60 minutes to dry. To complete three loads of laundry in this scenario would take 3.5 hours: 30 minutes for the first wash load and 60 minutes for the three dry cycles (after the first washing, all washings can occur concurrently with the drying).

Now, if the laundry room had two dryers and the clothes were moved between them every 30 minutes, it would take only 2.5 hours to complete three loads of wash: after 90 minutes each washer and dryer would be filled, and two more 30-minute cycles would empty the "pipeline."

In both scenarios, it takes 90 minutes for one load of wash to come out finished. However, the throughput of these scenarios are different: the first one can output a finished load every 60 minutes, while the second scenario can output a finished load every 30 minutes.

Such analogies aren't unheard of here: see Voltage#Hydraulic_analogy.

—Kairotic 16:08, 30 October 2006 (UTC)

I'm sorry, I can't follow your analogy, and I still don't get what pipelining is about. —Dudboi 13:02, 5 November 2006 (UTC)

That analogy isn't very good - try this instead: You have to wash, dry, and fold laundry. Washing takes 30 minutes; drying takes 60 minutes; folding takes 15 minutes. Without pipelining, you would wash a load, dry it, and fold it, and then wash the next load. That means that one load of laundry finishes every 105 minutes. With pipelining, once the first load has been washed, you start washing the next load of laundry. Once the first load has been dried, you start drying the second load, and the third load starts being washed. This way, a load finishes every 60 minutes (limited by the time it takes to dry). What Kairotic was trying to add to this was the idea that you could split the dryer into 2 steps, each of which takes half as long (that way, the longest step is just 30 minutes, and you would finish a load of laundry every 30 minutes). I wouldn't worry about that in the "simple" explanation of pipelining. --CTho 00:10, 6 November 2006 (UTC)

I removed the statements that pipelines increase latency. The time it takes to execute an instruction is the same whether or not a pipeline is used. The appearance of increased latency as 'the next instruction has to travel all the way through the pipeline before its result becomes available and the processor appears to "work" again' (to quote a line from the article) is an illusion. The next instruction has to travel all the way through the pipeline anyway; you just don't notice it when the pipeline is full since "work" is being done as the result of previous instructions. In terms of the cute animation, the time it takes to make each object is the same whether or not others are being worked on simultaneously. --Rick Sidwell 18:18, 10 Jan 2005 (UTC)

Pipelines don't increase latency? On the contrary, the latency is guaranteed to increase. In a non-pipelined process the latency is a single clock cycle. The single clock cycle's period is determined by the time to traverse all the logic involved in carrying out the instruction from the input registers to the output registers. With a pipelined process you have to go through all the same logic as well as all the pipeline registers, with the clock rate being determined by the pipeline stage with the greatest logic depth. (I'm including routeing in the logic depth here). In a non-pipelined process you are traversing less logic, and the clock rate is as high as the logic can handle. In a pipelined process you're traversing more logic, and most of it is being clocked slower than it could handle, due to all the pipeline stages having to use the same clock. Gantlord 14:33, 18 December 2006 (UTC)

The concept of pipelining is not that modern. 6502 of 1975 had pipelining. --matusz 11:03, 15 Mar 2005 (UTC)

Actually, it goes back a lot farther than that. The original pipelined computer was the IBM Stretch, conceived in 1955. NickP 13:01, 2 December 2005 (UTC)

[edit] double wikipedia entry

is this the same as Instruction pipelining?

Thanks for the heads up. I put merge tags on them. I expect that instruction pipelining will become a redirect to this page after any additional content in it has been absorbed into this article. Any volunteers? Deco 00:22, 27 May 2005 (UTC)

As I understand it, pipelining is a generic concept appliciable to many different things. Instruction pipelining is the way it's used in CPUs/GPUs etc to get some degree of parallelism. Therefore pipelining and instruction pipelining is not the same thing. Please correct me if I'm wrong. eKIK 19:57, 4 October 2005 (UTC)

Actually, imagine I have one pipeline which will change a value at the adress A. Before that happens maybe pipeline number 2 will already have worked with this value. So, pipeline number 2 already used a value that was not "finished" yet. Thus, aren't such collisions happening all the time when using instruction pipelining? Thanks, Abdull

I read through both articles, and theres no longer any reason to keep "Instruction Pipelining". IMO it should be deleted and the current "pipelineing" article should be renamed to "Instruction Pipelining" to distinquish it from "Software Pipelining" and other related applications of pipelining.

Less talking, more editing... The instruction pipeline article is totally redundant, and this one is of higher quality. I've set the other to redirect here. -- uberpenguin 02:51, 18 December 2005 (UTC)

[edit] last paragraph of first section

I don't think you need 4 independent instructions to keep a non-forwarding 5 stage pipeline full. Assuming 2 dependent ops, you get:

f d e m w
  f     d e m w

That's 2 stalls if you can read from the register file the same cycle you write it, otherwise 3.

--CTho 15:44, 26 December 2005 (UTC)

I think this is wrong: "Because each stage performs only a small part of the overall computation, clock speed can be increased tremendiously."

Pipelining increases the average number of instructions executed per clock cycle and not the clock speed itself.

"Think" what you like, but I know it typically increases the maximum clock speed too, as the inter-register logic depth is reduced. The minimum clock period is governed by the largest logic and routing delay between two registers within the pipeline. When you increase the number of stages in a pipeline, and assuming you're competent enough to balance the logic depths well, you decrease the minimum clock period and hence increase the maximum clock frequency. See the large numbers of stages present in the Prescott Pentium 4 and the resultant clock period increases. You can expect the cost of this to come in increased area requirements (those registers don't come free) and in higher power consumption (more logic, transitioning more often). Pipelining is good, but it's not magic, it's a way to trade power, area and latency for throughput. Gantlord 14:33, 18 December 2006 (UTC)

It does both.  Consider a single-cycle design vs a pipelined design - both have an IPC of ~1,
but the pipelined design can have a much higher clock speed.
--CTho 16:55, 27 December 2005 (UTC)

[edit] One stage pipeline?

The article states that the MOS Tech 6502 has a one stage pipeline, i thought that all pipes needed to be of size 2 or more. furthermore, there is no mention of any pipe in MOS Technology 6502 at all. This is seems odd 129.78.208.4 01:50, 1 March 2007 (UTC)