User:Hobit

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[edit] Interests

Gaming, Computer Science, Embedded systems, Comics.

[edit] Editing

I normally edit without being logged in. Most of my edits are at Rose-Hulman, but I do a LOT of spelling fixes and the like.

[edit] Tips on using the Verilog Tools

Compiler Warnings

I thought everyone should know that vcs (the verilog compiler) can provide some additional warnings beyond what the default makefile gives you, such as better detection of assignment width mismatches, and "too few port connections" (i.e. you haven't connected every port in a module instantiation) - both of which could be rather useful. To do this, add "+lint=all,noVCDE +warn=all" to the line near the top of your Makefile beginning with "VCS = ". (It still doesn't tell you such things as whether you're referencing an undeclared wire... if anyone knows how to make it care about such things, I'd love to hear from you) --Akgood 22:15, 21 Mar 2007 (EST)

   * Good point. Those additional messages can get overwhelming which is why we don't normally suggest it (I don't know what the noVCDE does). I also have some students working on a "warning generator" for Verilog. A beta version should be posted in the next week or so. --Brehob 22:44, 21 Mar 2007 (EST)
         o If you set "+lint=all" without ",noVCDE" then the compiler will generate a message each time it encounters a "`define" statement. Since there are lots of these in sys_defs.vh, it gets really annoying really fast. Maybe that's what you meant when you said the additional messages can get overwhelming... --Akgood 15:45, 24 Mar 2007 (EST) 

[edit] Making The Synthesizer Ignore code

I noticed while browsing around that this page (http://www.asic-world.com/verilog/assertions3.html) suggests a way to make the synthesizer ignore blocks of code. I haven't tried it, but it could be a good alternative or complement to using "`ifdef" statements to make debugging logic optional.

Here's how it works:

        ... (code, will be synthesized)
        // synopsys translate_off
        ... (code, will not synthesized)
        // synopsys translate_on
        ... (code, will be synthesized)

So anything between "// synopsys translate_off" and "// synopsys translate_on" won't be synthesized. As I said, I haven't tried it, so if you try it and it doesn't work, be sure to say so on this page... --Akgood 15:45, 24 Mar 2007 (EST) Retrieved from "http://wiki.eecs.umich.edu/eecs470_w07/index.php?title=Tips_on_using_the_Verilog_Tools"