GMII

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GMII is an acronym for Gigabit MII, interfaces are the backward compatible with the Media Independent Interface specification.

The GMII specification is used to define the interface between the Media Access Controller (MAC) device and the physical layer device (PHY). The interface defines speeds of 1000MBits per second, implemented using eight bit data interface clocked at 125MHz. It can also operate on fall-back speeds of 10/100 MBit as per the MII specification.

Data on the interface is framed using the IEEE Ethernet standard. As such it consists of a preamble, start of frame delimiter, Ethernet headers, protocol specific data and a cyclic redundancy code (CRC) checksum.

The GMII interface is defined in IEEE Standard 802.3, 2000 Edition [1]

1 Transmitter
- 1.1 Notes on transmit clocks
2 Receiver
3 Management
4 See also

[edit] Transmitter

GTXCLK - clock signal for gigabit TX.. signals (125MHz)
TXCLK - clock signal for 10/100 MBit signals
TXD[7..0] - data to be transmitted
TXEN - transmitter enable
TXER - transmitter error (used to corrupt a packet)

[edit] Notes on transmit clocks

There are two clocks, depending on whether the PHY is operating at gigabit or 10/100MBit speeds. For gigabit speeds, the GTXCLK is supplied to the PHY and the TXD,TXEN,TXER signals are synchronized to this. Otherwise for 10/100MBit the TXCLK (supplied by PHY) is used for synchronizing those signals. This operates at either 25MHz for 100MBit or 2.5MHz for 10MBit connections. The receiver clock is much simpler with only one clock which is recovered from the incoming data. Hence the GTXCLK and RXCLK are not coherent.

[edit] Receiver

RXCLK - received clock signal (recovered from incoming received data)
RXD[7..0] - received data
RXDV - signifies data received is valid
RXER - signifies data received has errors
COL - Collision Detect (half-duplex connections only)
CRS - Carrier Sense (half-duplex connections only)

[edit] Management

MDC - Management interface clock
MDIO - Management interface I/O bidirectional pin.

The management interface controls the behaviour of the PHY. There are 32 addresses, each containing 16 bits (the first 16 have a defined usage, see "IEEE 802.3,2000-22.2.4 Management Functions", the others are device specific). These registers can be used to configure the device (say "only gigabit, full duplex", or "only full duplex") or can be used to determine the current operating mode. (More information needed)