Flat memory model
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In computer programming, the flat memory model is an approach to organizing memory address space. In this model, a computer application uses a single address space for both program code memory and data memory. This is in contrast to the Harvard architecture used in early computing history, or the segmented memory architecture used in the Intel 80x86 family of microprocessors. On 16-bit processors, a flat memory model yields a maximum combined code/data size of just 64 kibibytes. 32-bit models can access a maximum of 4 gigabytes, while 64-bit processors can theoretically access an address space of 16 exbibytes.
[edit] Advantage over Harvard architecture
The flat memory model offers the advantage of programming simplicity over the other models mentioned above. A memory address is always unambiguous in the flat memory model, referring to a well-defined memory location. In contrast, a memory address the Harvard architecture requires an additional qualifier to distinguish a code address from a data address. This means added bookkeeping complexity for the programmer.
[edit] Advantage over segmented model
A similar complexity issue exists with the segmented memory model, as implemented on the now ubiquitous Intel 80x86 family of microprocessors. The segmented model divides a large memory address space into smaller chunks (called segments) that can be accessed by giving each chunk a unique number, called a selector. In order to do this, a special segment register is used to select the segment you wish to use, then the selected segment is made to look like a normal flat piece of memory. Using this configuration, a 16-bit microprocessor can access up to 4 gibibytes of memory (65536 segments of 65536 bytes). However, in real mode the arrangement of a Segmented Memory Model is where a 16-bit (64 KiB) addressing space is overlapped every 16 bytes (called a paragraph) in order to create a 1 mebibyte total addressing space.
In protected mode the lower 3 bits of a selector are NOT part of the index. Instead the first 2 bits are the Requested Privilege Level (RPL) of the selector, and the third bit tells the processor which table to look up. If it is zero, the index is in the GDT and if it is one, it is in the current LDT. The processor first checks the Descriptor Privilege Level (DPL) of the accessed segment against both the Current Privilege Level (CPL) and the selector's RPL and faults on access violations.
If not, the processor looks it up in whenever table the index it is in for the segment base, and if it is not found, it causes a fault. If it is found, it checks if the current operation done is allowed on the segment. If not it faults. If it is allowed, the processor adds the offset to the segment base to form a 24-bit or 32-bit physical address and performs the operation.
Note: Because the index is 13-bit, even in protected mode using a segmented memory model, if the maximum size of a segment is 64 KiB only 1 GiB of virtual memory can be accessed at one time (512 MiB global, 512 MiB local).
The advantage of the flat memory model is that applications running in such a model, unlike applications running in a segmented memory model, do not have to switch segments to access additional code or data. Furthermore, manipulating memory and data can be achieved with far fewer internal registers, as shown in the new generation of RISC microprocessors. This drastically simplifies processor architecture from a manufacturing point of view, compiler construction from a tool developer's point of view, and programming complexity from a programmer's point of view.
These simple benefits of the flat memory model have enabled microprocessors utilising the model to outperform microprocessors utilising segmented memory models where most other environmental factors (e.g. microprocessor clock speed and memory speed) are considered equal. Put another way, microprocessors utilising a flat memory model have often been shown to achieve equivalent performance of a processor utilising a segmented memory model despite the fact they are running slower clock speeds and have simpler (and cheaper) architectures.
