Talk:Field-programmable gate array

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[edit] Old / Random Notes

And why is there no discussion of the inherent emulator problems? (such as sequential software vs. parallel hardware) —The preceding unsigned comment was added by 66.194.87.250 (talk • contribs) on 21:05, 2 February 2006.

If the figures were made in xfig they can be improved by exporting to image format at 200% or more. Then scale image down if needed in gimp. —The preceding unsigned comment was added by Rtdrury (talk • contribs) on 08:33, 23 October 2005.

Curious why Agere/Lucent was deleted - Williamv1138 14:39, Aug 8, 2003 (UTC)

  • Their FPGA division was acquired by Lattice Semi, in 2001 I think. Cheese Sandwich 02:09, 17 August 2005 (UTC)

There's also FPGA (Flip Pin Grid Array), a type of CPU design. -- Tarquin 14:42, 8 Aug 2003 (UTC)

Well, a kind of packaging techonlogy, anyway. -- Anon. —The preceding unsigned comment was added by 217.158.229.59 (talk • contribs) on 14:48, 8 August 2003.

This article appears very xilinx-biased in terms of covering a fairly narrow range of FPGA devices, which have many different layouts from what I can tell (ie not all exactly as described). Might be nice to make it more general, or sprinkle a few "In one particular implementation..." type comments around. Mat-C 03:43, 21 Jun 2005 (UTC)

Part of this article reads like a programming manual: "Since the clock is normally routed via a special-purpose dedicated routing network in commercial FPGAs, do NOT route it or include it in your track count results. That is, you can completely ignore the clock net, since it is assumed to be routed on a special global network." I should be excused for thinking some indiscriminate copying has been done here. Radioflux 15:32, 21 September 2005 (UTC)

Would a section on the different design methodologies for fpga vs asic be welcome - e.g. extra use of registering (for speed) designing to available resources, tricks to fit functions into memories etc? Or is this too much detail/not appropriate to wikipedia? It also occured to me that the concepts of embedded vs distributed memory have been skipped over in this article, is something like this needed. How about contrasting the architecture of fpgas to cplds? . -- Rufty 16:57, 19 Aug 2005 (UTC)

I have made some substantial edits/additions to this page related to FPGA history, software tools and related device technologies. Probably more is needed related to design tools, and perhaps more complete links to external resources. I also agree that some of the architecture discussion is Xilinx-specific, but I didn't touch that part. Rudderpost 16:40, 4 November 2005 (UTC)

[edit] Typical Clock speeds

Nowhere does the article mention typical clock speeds for FPGA's - unless I missed it - could someone who is knowledgable add it please? --Wierdy1024 19:49, 4 June 2006 (UTC)

I think that's because the ranges are so large and it depends on the algorithm that is programmed in it. For example, a current generation core can likely exceed 200 MHz. However, that would be an extremely pipelined design, because there is always a tradeoff of space vs. speed - if you do more work in a single clock, it takes you longer, but if you do less work then you need to store more intermediate results. A much more complicated design may only hit 50 MHz in the same part. For I/O, both A and X have high speed I/O serdes that can exceed 10 Gbps, but internally the signal would be 64 bits wide (and therefore only 155 Mbps). -- RevRagnarok Talk Contrib Reverts 20:25, 4 June 2006 (UTC)

[edit] commercial links

This article is thick with commercial links. It seems like the "Some FPGA third-party tool suppliers with descriptions" and "Some FPGA manufacturers and their specialties" should be deleted altogether. -- Mikeblas 03:19, 6 July 2006 (UTC)

There are few enough manufacturers in the industry that I don't really see this being a problem. Your mileage may vary. I agree that the third-party tool vendor list is a bit long. --Christopher Thomas 03:34, 6 July 2006 (UTC)
I agree. As for tool vendors, the two biggest are the two biggest manufacturers, A and X. After that, as far as I know, are ModelSIM and Synplify. I was shocked to see Annapolis Micro in there, I dealth with them years ago, but I am <20 mi from them. -- RevRagnarok Talk Contrib Reverts 10:23, 6 July 2006 (UTC)
So now that 'nearly' every external link has been deleted, shall we have a discussion of what to have? Since there are so few FPGA manufacturers, my opinion is that we should definitely include those. Mrand 14:30, 26 November 2006 (UTC)
Not as list of external links, but as list with internal links to their articles. (Notability criterion: If they're not notable enough to have their own article, they're even less notable to get a link in this one.) WP articles are not an online business directory. Femto 15:34, 26 November 2006 (UTC)

[edit] "Combinational" vs. "Combinatorial"

I noticed somebody changed "combinational" to "combinatorial" - actually "combinational" is a perfectly acceptable term, and is used in the Altera Quartus II software. --Cheese Sandwich 12:24, 17 July 2006 (UTC)

I've never used or heard combinational until this discussion... only combinatorial. But when I google combinatorial combinational fpga, it appears that they are used almost interchangably. Mrand 13:06, 17 July 2006 (UTC)
Combinatorial is the term that I have used and have heard for about a decade now, so that's why I changed it back (and for some reason had been logged out). It's always been combinatorial vs. synchronous processes in VHDL that are being discussed among the engineers. The linked article's talk about "Enumerative combinatorics" seems to back it up - the synthesizer needs to compute every possible outcome from all possible inputs and then try to create a gate/CLB/slice/whatever combination equivalent. Now that I think about it, we may even want to make the word a link with an anchor to 'enumerative combinatorics.' — RevRagnarok Talk Contrib Reverts 13:07, 17 July 2006 (UTC)
The math term is "combinatorial". In digital design, the term is "combinational". Please refer to Carver_Mead and Lynn Conway's book which ushered in the VLSI era, Introduction to VLSI Systems. Also, Wikipedia redirects "combinatorial logic" to "combinational logic" rather than vice versa, so that's probably the right place to have this debate... until then the FPGA article ought to follow that convention. Megacz 19:32, 17 July 2006 (UTC)
Discussed among engineers on what continent? It's "combinational" in every reference I've encountered in North America. If Europe uses different conventions, that should probably be noted in the combinational logic article. --Christopher Thomas 23:37, 17 July 2006 (UTC)
The wonderful People's Republik of Merlin'. Maybe it's a VHDL vs Verilog terminology thing. ;) I even mentioned this article today at work and the 3 engineers I talked to all said "WTF? Of course it's combinatorial!" We are all contractors in gov't work (hence the VHDL). — RevRagnarok Talk Contrib Reverts 02:50, 18 July 2006 (UTC)
Maybe as a compromise we could write "combinational (combinatorial)" instead of "combinational", since both terms are used. --Cheese Sandwich 03:03, 18 July 2006 (UTC)
I'm with the three engineers who said "WTF?" With almost 30 years of experience in the business, I've always heard and said "conbinatorial". And I'm in North America. - Atlant 12:36, 18 July 2006 (UTC)
University of Toronto, ECE 1999+PEY. You have seniority on me, but I still count myself as qualified to comment. I've never heard "combinatorial" used for this context before seeing this talk page. Checking http://ieeexplore.ieee.org for published uses, "combinatorial logic" gets 58 citations, and "combinational logic" gets over 100 citations (list is limited to the first 100 hits). This suggests that while both are used by IEEE members, "combinational" is the more common term. --Christopher Thomas 18:22, 18 July 2006 (UTC)
More importantly, one of the major FPGA vendors' software uses "combinational" (in fact, they deliberately switched from "combinatorial" to "combinational" at one point). --Cheese Sandwich 18:27, 18 July 2006 (UTC)


[edit] Regarding switchboxes

I've read on the comp.arch.fpga newsgroup that there actually are no switchboxes in (at least) modern Xilinx devices. My feeling is that this has been true for quite some time but I don't have any good source on that though. See for example this posting on comp.arch.fpga: [1] --Ehliar 13:00, 12 January 2007 (UTC)

As far as I am concerned, routing resources are "magic." I think 'switch box' is just a way to explain the concepts of what is happening inside, not actually describing the physical layout. — RevRagnarok Talk Contrib 13:22, 12 January 2007 (UTC)
I don't really object to the description of the switch box as an explanation of the concept of routing. My main objection is that it sounds like almost all FPGAs function like that. "Generally, the FPGA routing is unsegmented." http://direct.xilinx.com/bvdocs/publications/ds031.pdf (page 41 in the PDF file) describes the routing resources in a Virtex-2. In that architecture it is very common with routing resources that terminate a couple of CLBs away from the sender. (And the same is true for all other Xilinx devices that I've used.) Perhaps the page should make it clear that it describes a conceptual view and not how it really looks like. --Ehliar 15:18, 12 January 2007 (UTC)
If you want to get picky, just write a section about Manhattan vs. Island style; however, this ruins the conceptual view approach as there are so many approaches. Xilinx, for example, varies between series how the routing is implimented. The complete article could be redone to discuss architecture from a circuit level approach for Xilinx-vs-Altera, etc; however, that's not really the point. There's 10-years of VPR papers discussion routing, and research papers publised by vendors which you'd have to include if you wanted to cover the subject in its entirity. I've found this article adquate to get students started. --Degs 18 January 2007
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