Talk:Emotion Engine

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Hey, I remember there was much panic in the press about Saddam and Kim of Korea using these EE chips stripped from PS2 consoles to make cheap precision cruise missile warheads and annule western military technology superiority. That could be discussed. 195.70.32.136 19:04, 13 March 2006 (UTC)

Be my guest (but cite references). Diceman 16:03, 14 March 2006 (UTC)

You could guide a cruise missile with a 6502. It isn't rocket science. Well, okay, technically, it is, but it doesn't require much CPU horsepower. ;) The concern about 'rogue states' getting supercomputers is that they would be able to do nuclear warhead simulation/design with them. However, I suspect you have to do some real-world nuke testing to know that your simulations are accurate -- in other words, you already have to be able to build a nuke, but a supercomputer can help you build a better/more compact/more efficient one. Today, surplus Pentium III CPUs might be a better bet for rogue state supercomputer development. Kaleja 05:21, 16 September 2006 (UTC)

[edit] Really a 128 bit processor?

Is this cpu >really< a 128 bit one? Some people think that ee is a 32 bit processor, and that the 128 bit thing is a marketing argument.

For instance, all pentium 3/athlon xp processors have 128 bit instructions (simd sse) but they remain being 32 bit processors. Isn't the same with the ee?

Licurgo 04:15, 5 June 2006 (UTC)

The MIPS R5900 core is 64 bits for sure, the vector units are probably 128 bits, but I don't think this qualify the EE as a 128 bit processor. --Pezezin 23:11, 28 June 2006 (UTC)

Well this should be reflected on the article, because it says 128 bits everywere and it isn't true. Thanks for answering. --Licurgo 03:24, 8 July 2006 (UTC)

The core register set has been extended from 64 to 128 bit width. A single instruction can do a 128-bit read or write. Pointer width is 32-bit; address space might be 64-bit but it's a moot point because there's quite a bit less than 4GB of addressable memory. The integer math unit is 64-bit (as stated in the article), and I can't say for sure what the internal bus widths are. It's very hard to boil a modern complex CPU down to a single number describing its bit width, but it's not pure marketingese to say that EE is 128-bit. Kaleja 05:12, 16 September 2006 (UTC)

[edit] FLOPS confusion

From the article it descibes a maximum of 14 FLOPS per clock. 14 FLOPS per clock * 294/299Mhz = 4.116/4.186 GigaFLOPS not 6.2. whats up with that? Also from my understanding a 733 Mhz PIII with one vec4 unit and and one scalar FPU has a max of 3.665 GigaFLOPS, not hardly one half the FLOPS power, and combinded in to a single thread ,and WAY less total instructions per clock, to boot. However that doesnt count in the poor implementation of MMX in the PIII, but this about theoretical numbers. and the 400mhz Celeron would have to be PII based to be anywhere close to that slow.