Emotion Engine

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Sony Emotion Engine CPU

The Emotion Engine is the name of the Central Processing Unit (CPU) used in Sony PlayStation 2 video game consoles. It was jointly designed by Toshiba and Sony and began mass production in 1999. According to MicroDesign Resources, it is two times the speed of a 733 MHz Pentium III and 15 times the speed of a 400 MHz Celeron at handling tasks like full-motion video (SIMD). [1]

The Emotion Engine's data bus, cache memory as well as all registers are implemented in 128 bit technology, integrated on a single 0.18 micrometer process technology chip (making it the first commercial 128 bit CPU). The Emotion Engine, based on the MIPS R5900, is sort of a combination CPU and DSP processor, whose main function is simulating 3D worlds. It integrated all necessary units on the die: The MIPS III CPU core, 2 vector units, FPU, image processing unit (basically an MPEG2 decoder with some other capabilities), 10-channel DMA controller, graphics interface unit, RDRAM and I/O interfaces, all connected via a shared 128-bit internal bus.

The chip is also used in early Playstation 3 units to achieve backwards compatibility and as shading/rasterization offload point for additional or post processing of complex PS3 specific games. PAL Playstation 3 units do not include an Emotion Engine as a matter of cost-saving, however this means such units must use less reliable software emulation to achieve some level of backwards compatibility. It is believed that eventually a hardware revision of NTSC units will remove the Emotion Engine chip in these territories.

1 Specifications
2 Clock and Bus speed
3 See also
4 External links

[edit] Specifications

CPU core: 128-bit RISC (MIPS IV-subset)
Clock Frequency: 294 MHz (299 MHz in later versions)
Gate width: 0.18 µm
V_DD Voltage: 1.8 V
Power consumption: 15 W
Metal layers: 4
Total transistors: 10.5 million
Die size: 240 mm²
Package: 540 pin PBGA
Integer Unit: 64-bit (2-way Superscalar)
Multimedia extended instructions: 107 instructions at 128 bit width
Integer General Purpose Register: 32 at 128 bit width
TLB: 48 double entries
Instruction Cache: 16 KB (2 way)
Data Cache: 8 KB (2 way)
Scratch pad RAM: 16 KB (Dual port)
Main Memory: 32 MB (Direct RDRAM 2 channels at 800 MHz)
Memory bandwidth: 3.2 GB/s
DMA: 10 channels
Co-processor 1: FPU (FMAC x 1, FDIV x 1)
Co-processor 2: VU0 (FMAC x 4, FDIV x 1)
Vector Processing Unit: VU1 (FMAC x 5, FDIV x 2)
Floating Point Performance: 6.2 GFLOPS
Curved Surface Generation (Bezier): 16 million polygons per second
Image Processing Unit: MPEG2 Macroblock Layer Decoder
Image Processing Performance: 150 million pixels per second

Geometry

Perspective Transformation: 66 million polygons per second
Lighting: 38 million polygons per second
Fog: 36 million polygons per second

[edit] Clock and Bus speed

The execution units (the main core and both vector units) operate at the specified speed of ~300Mhz, and all three execution units can execute two instructions every cycle assuming no stalls occur.

The bus and peripheral interfaces operate at half the core speed.