Clock skew
From Wikipedia, the free encyclopedia
Contents |
[edit] In circuit design
In circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This is typically due to two causes. The first is material variability, which causes a signal to travel faster or slower than expected. The second is distance: The further a signal has to travel the longer it takes to arrive; therefore, signals will arrive at different points at different times. As the clock rate of a circuit increases timing becomes more critical and there is less variation that can be tolerated while still functioning properly.
Clock skew can cause harm in two ways. Suppose that a logic path travels through combinational logic from a source flip-flop to a destination flip-flop. If the destination flip-flop receives the clock tick later than the source flip-flop, and if the logic path delay is short enough, then the data signal might arrive at the destination flip-flop before the clock tick, destroying there the previous data that should have been clocked through. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through. If the destination flip-flop receives the clock tick earlier than the source flip-flop, then the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.
Clock skew, if done right, can also benefit a circuit. It can be intentionally introduced to decrease the clock period at which the circuit will operate correctly, and/or to increase the setup or hold safety margins. The optimal set of clock delays is determined by a linear program, in which a setup and a hold constraint appears for each logic path. In this linear program, zero clock skew is merely a feasible point.
[edit] On a network
On a network such as the internet, clock skew describes the difference in time shown by the clocks at the different nodes on the network. It is usually an unavoidable phenomenon (at least if one looks at milli-second resolutions), but clock skew of tens of minutes or more is also quite common. A number of protocols (e.g. Network Time Protocol) have been designed to reduce clock skew, and produce more stable functions.
[edit] See also
[edit] References
- Friedman, E.G., ed., Clock Distribution Networks in VLSI Circuits and Systems, IEEE Press, 1995.
- Maheshwari, N., and Sapatnekar, S.S., Timing Analysis and Optimization of Sequential Circuits, Kluwer, 1999.
- Tam, S., Limaye, D.L., and Desai, U.N., "Clock Generation and Distribution for the 130-nm Itanium 2 Processor with 6-MB On-Die L3 Cache", in IEEE Journal of Solid-State Circuits, Vol. 39, No. 4, April 2004.
In addition, there are hundreds of articles on various technical details of this subject (Clock skew). These are normally presented at conferences such as the Design Automation Conference (DAC) and the International Conference on Computer-Aided Design (ICCAD), along with many smaller conferences. The main journal in the field is IEEE Transactions on Computer-Aided Design. Most of these journals and conference proceedings are published by the IEEE or the ACM. You can search the IEEE on-line library and the ACM digital library and view the abstracts for free. Downloading full text requires purchase, society membership, or a site license; many schools and companies have such licenses already.
