Chip-level multiprocessing

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In computing, chip-level multiprocessing (also known as chip multiprocessor, CMP) is symmetric multiprocessing (SMP) implemented on a single VLSI integrated circuit. Multiple processor cores (multicore) typically share a common second- or third-level cache and interconnect.

The goal of a CMP system is to allow greater utilization of thread-level parallelism (TLP), especially for applications that lack sufficient instruction-level parallelism (ILP) to make good use of superscalar processors.

The latest versions of many architectures use CMP, including PA-RISC (PA-8800), IBM POWER (POWER4 and POWER5), SPARC (UltraSPARC IV), and various processors from Intel and AMD.

There is some controversy as to whether multiple cores on a chip is the same thing as multiple processors. Major technology providers are divided on this issue. IBM considers its dual-core POWER4 and POWER5 to be two processors, just packaged together. Sun Microsystems, in contrast, considers its UltraSPARC IV to be a multi-threaded rather than multi-processor chip. Intel considers their CMP designs to be a single processor. This is not an idle debate, because software is often more expensive when licensed for more processors.

In October 2004, Microsoft announced that it would treat multicore chips as "1 processor" rather than "N processor" chips for purposes of licensing its server software. Microsoft made no specific declaration regarding its desktop software (including its widely used Microsoft Windows and Microsoft Office products), but presumably it would license them similarly. While Microsoft's decision is the opposite of that made by important competitors such as Oracle Corporation and IBM's Software Group, many other independent software vendors have yet to declare their approach; many are likely to follow Microsoft's lead, given its bellwether status.

However a processor manufacturer, software vendor, or user would like to treat a CMP chip for licensing and marketing purposes, symmetric multiprocessing (SMP) operating systems are required to take full advantage of CMP chips. That is, the OS—the entity responsible for scheduling and coordinating system resources—must do the exact same work for CMP chips as it does for discrete multiple processors.