Channel I/O
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In computer science, channel I/O is a generic term that refers to an advanced, high-performance input/output architecture that is implemented in various forms on a number of computer architectures, especially on mainframe computers. In the past they were generally implemented with a custom processor, known alternately as peripheral processors, I/O processors, I/O controllers or DMA controllers.
Many input/output tasks can be fairly complex and require logic to be applied to the data to convert formats and other similar duties. In these situations the computer's CPU would normally be asked to handle the logic, but due to the fact that the I/O devices are very slow, the CPU would end up spending a huge amount of time (in computer terms) sitting idle waiting for the data from the device. A channel I/O architecture avoids this problem by using a low-cost processor with enough logic and memory onboard to handle these sorts of tasks. They are typically not powerful or flexible enough to be used as a computer on their own, and are actually a form of co-processor. The CPU sends small programs to the controller to handle an I/O job, which the channel controller can then complete without any help from the CPU. When it is complete, or there is an error, the channel controller communicates with the CPU using a selection of interrupts. Since the channel controller has direct access to the main memory of the computer, they are also often referred to as DMA Controllers (where DMA means direct memory access), but that term is somewhat more loose in definition and is often applied to non-programmable devices as well.
The first use of channel controllers was in the famed CDC 6600 supercomputer, which used 12 dedicated computers they referred to as peripheral processors, or PP's for this role. The PP's were quite powerful, basically a cut down version of CDC's first computer, the CDC 1604. Since the 1960s channel controllers have been a standard part of almost all mainframe designs, and the primary reason why anyone buys one. Channel controllers have also been made as small as single-chip designs with multiple channels on them, used in the NeXT computers for instance. However with the rapid speed increases in computers today, combined with operating systems that don't "block" when waiting for data, the channel controller has become somewhat redundant and are not commonly found on smaller machines.
Channel controllers can be said to be making a comeback in the form of "bus mastering" peripheral devices, such as SCSI adaptors and network cards. The rationale for these devices is the same as for the original channel controllers, namely off-loading interrupts and context switching from the main CPU.
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[edit] Description
The reference implementation of channel I/O is that of the IBM System/360 family of mainframe computers and its successors, but similar implementations have been adopted by other mainframe vendors, such as Control Data, Bull (General Electric/Honeywell) and Unisys.
Computer systems that use channel I/O have special hardware components that handle all input/output operations in their entirety independently of the systems' CPU(s). The CPU of a system that uses channel I/O typically has only one machine instruction in its repertoire for input and output; this instruction is used to pass input/output commands to the specialized I/O hardware in the form of channel programs. I/O thereafter proceeds without intervention from the CPU until an event requiring notification of the operating system occurs, at which point the I/O hardware signals an interrupt to the CPU.
A channel is an independent hardware component that coordinates all I/O to a set of controllers or devices. It is not merely a medium of communication, despite the name; it is an intelligent hardware device that handles all details of I/O after being given a list of I/O operations to carry out (the channel program).
Each channel may support one or more controllers and/or devices. Channel programs contain lists of commands to the channel itself and to various controllers and devices to which it is connected. Once the operating system has prepared a complete list of I/O commands, it executes a single I/O machine instruction to initiate the channel program; the channel thereafter assumes control of the I/O operations until they are completed.
It is possible to develop very complex channel programs, initiating many different I/O operations on many different I/O devices simultaneously. This flexibility frees the CPU from the overhead of starting, monitoring, and managing individual I/O operations. The specialized channel hardware, in turn, is dedicated to I/O and can carry it out more efficiently than the CPU (and entirely in parallel with the CPU). Channel I/O is not unlike the Direct Memory Access (DMA) of microcomputers, only more complex and advanced. Most mainframe operating systems do not fully exploit all the features of channel I/O.
On large mainframe computer systems, CPUs are only one of several powerful hardware components that work in parallel. Special input/output controllers (the exact names of which vary from one manufacturer to another) handle I/O exclusively, and these in turn are connected to hardware channels that also are dedicated to input and output. There may be several CPUs and several I/O processors. The overall architecture optimizes input/output performance without degrading pure CPU performance. Since most real-world applications of mainframe systems are heavily I/O-intensive business applications, this architecture helps provide the very high levels of throughput that distinguish mainframes from other types of computer.
[edit] Channel command words
A channel command word (CCW) is a command used to initiate an I/O operation on a channel-attached device, such as “read” or “seek”.
In IBM ESA/390 terminology, a channel is a parallel data connection inside the tree-like or hierarchically organized I/O subsystem. In System/390 I/O cages, channels either directly connect to devices which are installed inside the cage (communication adapter such as ESCON, FICON, open systems adapter or they run outside of the cage, below the raised floor as cables of the thickness of a thumb and directly connect to channel interfaces on bigger devices like tape subsystems, direct access storage devices (DASDs), terminal concentrators and other ESA/390 systems.
[edit] Channel programs
CCWs are organized into channel programs by the operating system or by standalone software (such as test and diagnostic programs). The CPU architecture of systems that use channel I/O typically provides only one machine instruction for all input and output, and this instruction, when executed, simply sends a signal to a dedicated input/output processing unit (e.g., a system assist processor, on IBM systems), which then assumes responsibility for all requested I/O. The main CPU of the system is then free to do other work. When the requested I/O operations result in an event or condition that requires the attention of the operating system, the input/output processor sends a signal to the CPU to cause an interrupt that the operating system can service.
Channel I/O provides considerable economies in input/output. For example, on IBM's Linux/390, the formatting of an entire track of a DASD requires only one channel program (and thus only one I/O instruction). The program is executed by the system assist processor (IBM's input/output processor) while the application processor (main CPU) is free for other work.
On system architectures that implement channel I/O, typically all devices are connected by channels, and so all I/O requires the use of channel programs.
[edit] Bootloading with channel I/O
Even bootloading (IPL, in IBM systems) of the system is carried out by channels: to load the system, a very small, simple program is loaded into memory and initiated, and this program causes the first portion of loading software to be loaded. The software is then executed when an interrupt is signaled to the CPU once the I/O is completed.
