Branch delay slot
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In computer architecture, a branch delay instruction is an instruction immediately following a conditional branch instruction which is executed whether or not the branch is taken. The location of such an instruction in the pipeline is called a branch delay slot. Branch delay slots are found not only in several RISC architectures including MIPS, PA-RISC and SPARC but also in DSP architectures including µPD77230 and TMS320C3x.
The goal of a pipelined architecture is to keep the pipeline full of instructions at all times. The branch delay slot is a side-effect of pipelined architectures due to the branch hazard, i.e. the fact that the branch would not be resolved until the instruction has worked its way through the pipeline. A simple design would insert stalls into the pipeline after a branch instruction until the new branch target address is computed and loaded into the program counter. Each cycle where a stall is inserted is considered one branch delay slot. A more sophisticated design would execute program instructions which are not dependent on the result of the branch instruction. This optimization can be performed in software at compile time by moving instructions into branch delay slots in the in-memory instruction stream, if the hardware supports this. Another side-effect is that special handling should be taken care of managing breakpoint on instructions as well as stepping while debugging within branch delay slot.
The number of branch delay slots in a particular pipeline implementation is dictated by the number of pipeline stages, the presence of register forwarding, what stage of the pipeline the branch conditions are computed, whether or not a branch target buffer (BTB) is used and many other factors.
By using branch prediction techniques and speculative execution, many of these branch delay slots are efficiently utilitized, reducing the performance penalty incurred by these branch instructions.
