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Itanium 2
Central processing unit

Itanium 2 processor
Produced: From mid 2002 to present
Manufacturer: Intel
CPU Speeds: 200 MHz to 1.6 GHz
FSB Speeds: 200 MHz to 533 MHz
Instruction Set: IA-64
Cores:
  • McKinley
  • Madison
  • Hondo
  • Deerfield
Itanium 2 logo
Itanium 2 logo

Itanium is the brand name for 64-bit Intel Microprocessors that implement the Intel Itanium architecture. Intel has released two processor families using the brand: Itanium and Itanium 2. The processors are marketed for use in enterprise-class multiprocessor computer systems. After a long development process, the first Itanium was released in 2001, and progressively more powerful Itanium processors have been released periodically since then. Most Itanium-based systems are produced by Hewlett-Packard (HP), the originator of the architecture, but several other manufacturers have developed systems based on Itanium. As of 2007 Itanium is the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, Power, and Sparc. Deployments have increased steadily since its introduction. Intel released its newest Itanium 2, called Montecito, in July 2006.

Contents

[edit] History

By 1989, HP had determined that RISC architectures were approaching a processing limit at one instruction per clock cycle. HP researchers investigated a new architecture called EPIC (Explicitly Parallel Instruction Computing) that allows the processor to execute multiple instructions in one clock cycle. EPIC implements a form of VLIW, where one instruction word contains multiple instructions. With EPIC, the compiler determines in advance which instructions can be executed at the same time, so the microprocessor simply executes the instructions and does not need elaborate mechanisms to determine which instructions to execute in parallel.[1]

HP decided that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors, so HP partnered with Intel in 1994 to develop the IA-64 architecture, which derived from EPIC. Intel was willing to undertake a very large development effort on IA-64 in the expectation that the resulting microprocessor would be used by the majority of the enterprise systems manufacturers. A three-year development effort was undertaken. By 1997, most enterprise systems manufacturers (with the exception of Sun) were designing systems based on the Intels's projected IA-64 processor, and Intel, HP[2], and industry analysts were predicting that IA-64 would dominate in servers, workstations, and high-end desktops, and eventually supplant RISC and CISC for all general-purpose applications. Several groups began to develop operating systems for the architecture, including a Linux variant and several UNIX variants.

By 1997, it was apparent that the IA-64 architecture and the compiler were much more difficult to implement than originally thought, and the delivery date began slipping quarter by quarter.[3].

Intel announced the name of the processor, Itanium, in October of 1999.[4] The schedule slips led some observers to begin using the term Itanic to refer to the processor immediately thereafter. The term refers to Titanic, the infamous ocean liner which sank in 1912. It was coined in a USENET post[5] and has often been used since then by The Register,[6] Scott McNealy,[7] and others.[8] It alludes to the perception that Itanium is a white elephant which cost Intel and partner Hewlett-Packard many billions of dollars while failing to achieve expected performance and sales in the originally projected timeframe.

Meanwhile, RISC and CISC architects were making steady improvements in superscalar implementations, allowing them to break the one-instruction-per-clock barrier without using EPIC. By the time Itanium was released in 2001, it was no longer superior to contemporaneous RISC and CISC processors. In 2001, Itanium competed at the low-end (primarily 4-CPU and smaller systems) with servers based on Intel IA-32, and at the high end with IBM's POWER architecture and Sun Microsystems' SPARC architecture. Intel repositioned Itanium to break into high-end business and technical computing, in the hopes of duplicating x86's successful "horizontal" (i.e., single architecture, multiple systems vendors) market. Its success was limited to a replacement for PA-RISC and Alpha in HP's "vertical" systems and MIPS in SGI's HPC focused servers. Adding to its failure to unseat POWER and SPARC was another complication: the 32-bit x86 architecture's growth into the enterprise space. Given its existing economies of scale fueled by its enormous installed base, x86 was the preeminent "horizontal" architecture in enterprise computing. HP and Intel recognized that Itanium was not competitive and replaced it with Itanium 2 a year later, as they had planned. Only a few thousand of the original Itaniums were sold, due to limited availability caused by poor yields, relatively poor performance, and high cost. However, these machines were useful for software development for the Itanium 2 processors that followed. The Itanium 2 was released in 2002, and was marketed for enterprise servers rather than for the whole gamut of high-end computing.

The biggest change in the competitive landscape has been the emergence of the x86-64 64-bit architecture, created by AMD and first implemented in the Opteron in 2003. Opteron gained rapid acceptance in the enterprise server space because it provided an easy upgrade from IA-32. Intel responded by implementing x86-64 in its Xeon microprocessors in 2004.[9]

In March, 2005, Intel announced that it was working on a new Itanium device, codenamed Tukwila, to be released in 2007. Tukwila would have four processors, and would replace the Itanium bus with a new Common System Interface, which would also be used by a new Xeon.[10] Intel later said that Tukwila would be delivered in late 2008.

As of March 2007, Intel has released seven additional versions of the Itanium 2, and another is expected in late 2007.

[edit] Intel Itanium Architecture

The Intel Itanium architecture.
The Intel Itanium architecture.

Intel has extensively documented the architecture.[11] The Architecture has been renamed several times during its history. HP called it EPIC and renamed it to PA-Wide-word. Intel later called it IA-64, before settling on Intel Itanium Architecture, but it is still widely referred to as IA-64. It is a 64-bit register-rich explicitly-parallel architecture. The base data word is 64 bits, byte-addressable. The logical address space is 264 bytes. The architecture implements predication, speculation, and branch prediction. It uses a hardware register renaming mechanism rather than simple register windowing for parameter passing. The same mechanism is also used to permit parallel execution of loops.

Speculation, prediction, predication, and renaming are under control of the compiler: each instruction word includes extra bits for this. This approach is the distinguishing characteristic of the architecture.

[edit] Registers

The architecture implements 128 Integer registers, 128 Floating point registers, 64 1-bit predicates, and eight branch registers. The floating point registers are 82 bits long to preserve precision for intermediate results.

[edit] Instruction execution

Each instruction word contains three instructions, and the fetch mechanism can read up to two instruction words per clock into the pipeline. When the compiler can take maximum advantage of this, the processor can execute six instructions per clock cycle. The processor has thirty functional execution units in eleven groups. Each unit can execute a particular subset of the instruction set, and each unit executes its instruction in one cycle unless it stalls waiting for data. While not all units in a group execute identical subsets of the instruction set, common instructions can be executed in multiple units. The groups are:

  • Six general-purpose ALUs, two integer units, one Shift unit
  • Four data cache units
  • Six multimedia units, two parallel shift units, one parallel multiply, one population count
  • two FMACs, two FMISCs
  • three branch units

Thus, the compiler can often group instructions into sets of six that can execute at the same time. Since the floating-point units implement a multiply/accumulate, a single floating point instruction can perform the work of two instructions when the application requires a multiply followed by an add: this is very common in scientific processing. When it occurs, the processor can execute four FLOPs per cycle.

[edit] Memory Architecture

From 2002 to 2006, Itanium 2 processors shared a common cache hierarchy. They had 16 KiB of Level 1 instruction cache and 16 KiB of Level 1 data cache. The L2 cache was unified (both instruction and data) and is 256 KiB. The Level 3 cache was also unified and varied in size from 1.5 MiB to 24 MiB. The 256Kib L2 cache contains sufficient logic to handle semaphore operations without disturbing the main ALU.

Main memory is accessed through a bus to an off-chip chipset. The Itanium 2 bus was initally called the McKinley bus, but is now usually referred to by Intel's official name: the Scalability Port. The speed of the bus has increased steadily with new processor releases.

[edit] IA-32 Support

Itaniums released prior to 2006 had hardware support for the IA-32 architecture to permit support for legacy server applications. Performance was disappointing. In 2005 Intel developed a software emulator that provided better performance. With Montecito, Intel removed IA-32 support from the hardware.

[edit] Architectural changes

With Montecito, Intel made enhancements to the architecture in July 2006.[12]

The architecture now includes Hardware multithreading: each processor maintains context for two threads of execution. When one thread stalls due to a memory access the other thread gains control. Intel calls this "coarse multithreading" to distinguish it from "hyperthreading technology" that was used in some x86 and x86-64 microprocessors. Coarse multithreading is well matched to the Intel Itanium Architecture and results in an appreciable performance gain.

Intel has also added hardware support for Virtualization. Virtualization allows a software "hypervisor" to run multiple operating system instances on the processor concurrently.

Montecito also features a split L2 cache, adding a dedicated 1MiB L2 cache for instructions and converting the original 256 KiB L2 cache to a dedicated data cache.

[edit] Hardware support

As of 2007, several manufacturers offer Itanium 2 based systems, including HP, SGI, NEC, Fujitsu, Unisys, Hitachi, and Groupe Bull. HP, the only one of the industry's top four server manufacturers to offer Itanium-based systems today, sells 90 percent of all Itanium 2 systems shipped. HP sold 7200 systems in the first quarter of 2006.[13] The bulk of the sales are of enterprise servers and machines for large-scale technical computing, with an average selling price per system in excess of $200,000 USD. A typical system uses tens to hundreds of Itanium processors.

Many of these vendors joined with Intel and a number of software vendors to form the Itanium Solutions Alliance [14], with the goal of promoting the architecture and collaborating to accelerate software porting. The Alliance announced that its members have committed to invest $10 Billion in Itanium solutions by the end of the decade.[15]

[edit] Chipsets

The Itanium bus interfaces to the rest fo the system via a chipset. Enterprise server manufacturers differentiate their systems by designing and developing chipsets that interface the processor to memory, interconnections, and peripheral controllers. The chipset is the heart of the system-level architecture for each system design. Development of a chipset costs tens of millions of dollars and represents a major commitment to the use of the Itanium. Currently, modern chipsets are manufactured by HP, Fujitsu, SGI, NEC, Hitachi, and Unisys. IBM created a chipset in 2003, and Intel in 2002, but neither of them has developed chipsets to support newer technologies such as DDR2 or PCI Express.[16]

[edit] Software support

In order to allow more software to run on the Itanium, Intel supported the development of effective compilers for its platform, especially its own suite of compilers. [17][18] GCC is also able to produce machine code for Itanium. [19][20] As of early 2007, Itanium is supported by Windows Server 2003, multiple distributions of Linux (including RedHat and Novell SuSE,) and HP-UX and OpenVMS from HP, all natively. It also supports mainframe environment GCOS from Groupe Bull and several IA-32 operating systems via Instruction Set Simulators. According to the Itanium Solutions Alliance, as of early 2007 over 10,000 applications are available for Itanium based systems.[21] The ISA also supports Gelato, an Open source community that ports and supports software for Itanium.[22]

[edit] Competition

The Itanium 2 competes in the enterprise server market. Itanium's major competitors include Sun Microsystems' UltraSPARC T1 and UltraSPARC IV+, IBM's Power 5+, AMD's Opteron, and Intel's own Xeon servers. In general, Itanium competes against Sun, IBM systems, and Opterons for running enterprise-class workloads on large, multi-processor servers in the back-end of corporate datacenters. It competes against Opteron and Xeon-based servers in smaller configurations and in cluster configurations.

Throughout its history, Itanium has had the best floating point performance relative to fixed-point performance of any general-purpose microprocessor. This capability is useful in HPC systems but is not needed for most enterprise server workloads. Sun's latest server-class microprocessor, the UltraSPARC T1 acknowledges this explicitly, with performance dramatically skewed toward the improvement of integer processing at the expense of floating point performance (eight integer cores share a single FPU). Thus Itanium and Sun appear to be addressing separate subsets of the market. By contrast, IBM's Cell microprocessor, with a single general-purpose POWER core controlling eight simpler cores optimized for floating point, may eventually compete against Itanium for floating-point workloads.

[edit] Supercomputers

Two computers based on Itanium 2 appeared in the top 10 of the November 2006 list[23] of the TOP500 supercomputers:

  • #7 Tera-10, Commissariat a l'Energie Atomique (CEA), France. Machine: Bull SMP Cluster, NovaScale 5160. CPU: 8,704 Itanium 2 (1.6 GHz). Connection: Quadrics QsNet II. Main Memory: 26112 GB. Rmax: 52.9 Teraflops.[24]
  • #8 Columbia, NASA Ames Research Center United States SGI Altix 3700, CPU: 10160 Itanium 2 (1.5 GHz). Connection: Voltaire Infiniband Rmax: 51.8 Teraflops.[25]

The best position ever achieved by an Itanium 2 based system in the list was #2, achieved in June 2004 when Thunder (LLNL) entered the list with an Rmax of 19.94 Teraflops. In November 2004 Columbia entered the list at #2 with 51.8 Teraflops.

The peak number of Itanium-based machines on the list occurred on the November 2004 list at 16.8%. In November 2006 the number is 7.0%

[edit] Processors

[edit] Released processors

The Itanium processors show a steady progression in capability. Merced was a proof of concept. McKinley dramatically improved the memory hierarchy and allowed Itanium to become reasonably competitive. Madison, with the shift to a 130nm process, allowed for enough cache space to overcome the major performance bottlenecks. Montecito, with a 90nm process, allowed for a dual-core implemenation and a major improvment in performance per watt.

Codename process released Clock L2 Cache L3 Cache Front Side
Bus		 dies/
device		 cores/
die		 watts/
device		 comments
Itanium
Merced 180nm June, 2001 733MHz 96KiB 3MiB* 133Mhz 1 1 ? off-die L3 cache
180nm June, 2001 900MHz 96KiB 4MiB* 133Mhz 1 1 ?
Itanium 2
McKinley 180nm July 8, 2002 900MHz 256KiB 1.5MiB 200Mhz 1 1 130 first HW support for branchlong
180nm July 8, 2002 1GHz 256KiB 3MiB 200Mhz 1 1 130
Madison 130nm June 30, 2003 1.3GHz 256KiB 3MiB 200Mhz 1 1 130
130nm June 30, 2003 1.4GHz 256KiB 4MiB 200Mhz 1 1 130
130nm June 30, 2003 1.5GHz 256KiB 6MiB 200Mhz 1 1 130
130nm September 8, 2003 1.4GHz 256KiB 1.5MiB 200Mhz 1 1 130
130nm April, 2004 1.4GHz 256KiB 3MiB 200Mhz 1 1 130
130nm April, 2004 1.6GHz 256KiB 3MiB 200Mhz 1 1 130
Deerfield 130nm September 8,2003 1.0GHz 256KiB 1.5MiB 200Mhz 1 1 62 Low voltage
Hondo 130nm early 2004 1.1GHz 256KiBx2 4MiBx2 200Mhz 2 1 260 32Mib L4
Fanwood 130nm November 8, 2004 1.6GHz 256KiB 3MiB 266Mhz 1 1 130
130nm November 8, 2004 1.3GHz 256KiB 3MiB 200Mhz 1 1 62? Low voltage
Madison 9M 130nm November 8, 2004 1.6GHz 256KiB 9MiB 200Mhz 1 1 130
130nm July 18, 2005 1.67GHz 256KiB 6MiB 333Mhz 1 1 130
130nm July 18, 2005 1.67GHz 256KiB 9MiB 333Mhz 1 1 130
Montecito 90nm July 18, 2006 1.4GHz 256KiB+1MiB 12MiBx2 400Mhz 1 2 104 Virtualization,
Multithread
90nm July 18, 2006 1.6GHz 256KiB+1MiB 12MiBx2 533Mhz 1 2 104

[edit] Future processors

Current event marker This article contains information about a scheduled or expected future product.
It may contain preliminary or speculative information, and may not reflect the final version of the product.

The future of the Itanium family apparently lies in multi-core chips, based on available information about coming generations. the final products will most likely bear the Itanium brand, possibly as Itanium 3 or perhaps just Itanium 2. As of March 2007, some information is known for the following:

  • Montvale will be a revision of Montecito bringing higher clock speeds, larger caches, and a faster FSB. Release is expected in late 2007.[26]
  • Tukwila, the first 65 nanometer design, is due in late 2008[27]. Tukwila will have 4 cores, with each core being multithreaded. It will feature a new bus called Common System Interface and an on-die memory controller.
  • For Poulson, few details are known other than the existence of the codename.

[edit] Timeline

Itanium Server Sales forecast history.
Itanium Server Sales forecast history.
  • 1989:
    • HP begins investigating EPIC[1]
  • 1994:
    • HP and Intel annouce partnership
  • 1997
    • June: IDC predicts IA-64 systems sales will reach $38BN/yr by 2001[28]
    • October: Dell announces it will use IA-64[29]
  • 1998
    • June: IDC predicts IA-64 systems sales will reach $30Bn/yr by 2001[28]
    • IBM announces it will build IA-64 machines[30]
    • October: Project Monterey is formed to create a common UNIX for IA-64
  • 1999:
    • February: Project Trillian is formed to create port Linux to IA-64
    • August: IDC predicts IA-64 systems sales will reach $25Bn/yr by 2002[28]
    • October: Intel Announces the Itanium name.
    • October: the term Itanic is first used
  • 2000:
    • February: Project Trillian delivers source code
    • June: IDC predicts Itanium systems sales will reach $25Bn/yr by 2003[28]
  • 2001:
  • 2002:
    • March: IDC predicts Itanium systems sales will reach $5Bn/yr by end 2004[28]
    • June:Itanium 2 is released
  • 2003:
    • April: IDC predicts Itanium systems sales will reach $9Bn/yr by end 2007[28]
    • April: AMD releases Opteron, a competing 64-bit microprocessor
    • June: Intel releases the "Madison" Itanium 2
  • 2004:
    • June: Intel releases a 64-bit Xeon
    • June: Thunder, a system at LLNL with 4096 Itanium 2 processors, is listed on on the TOP500 list at position #2.[32]
    • November: Columbia, an SGI Altix 3700 with 10160 Itanium 2 processors at NASA Ames Research Center, is listed on the TOP500 list at position #2.[25]
    • December: Itanium system sales for 2004 reach $1.4Bn
  • 2005:
    • January:HP ports OpenVMS to Itanium[33]
    • February: IBM server design drops Itanium support[34][16]
    • June: An Itanium 2 sets a record SPECfp2000 result of 2,801[35] in a Hitachi, Ltd. Computing blade.
    • September:Itanium Solutions Alliance is formed[36]
    • September: Dell exits the Itanium business[37]
    • October: Itanium server sales reach $619M/quarter in the third quarter.
    • October: Intel announces one-year delays for Montecito, Montvale, and Tukwila[38]
  • 2006:
    • January: Itanium Solutions Alliance announces a $10Bn collective investment in Itanium by 2010
    • February: IDC predicts Itanium systems sales will reach $6.6Bn/yr by 2009[39][40][41]
    • June: Intel releases the dual-core "Montecito" Itanium 2[42]

[edit] References

  1. ^ a b Inventing Itanium: How HP Labs Helped Create the Next-Generation Chip Architecture. HP Labs (June 2001). Retrieved on 2007-03-23.
  2. ^ De Gelas, Johan (November 9th, 2005). Itanium-Is there light at the end of the tunnel?. AnandTech. Retrieved on 2007-03-23.
  3. ^ Hodgin, Rick (6/4-8/2001). Intel's Itanium. geek.com. Retrieved on 2007-03-24.
  4. ^ Intel announces Itanium. domain-b.com (6 October 1999). Retrieved on 2007-03-28.
  5. ^ archived USNET post
  6. ^ Magee, Mike (29th October 1999). Intel execs outline Y2K chip futures. The Register. Retrieved on 2007-03-24.
  7. ^ Berlind, David (November 30, 2001). Interpreting McNealy's lexicon. ZDNet Tech Update. Retrieved on 2007-03-19.
  8. ^ Demerjian, Charlie (18 July 2006). Itanic shell game continues. The Inquirer. Retrieved on 2007-03-19.
  9. ^ Shankland, Stephen (December 7, 2005). Itanium: A cautionary tale. ZDNet News. Retrieved on 2007-03-17.
  10. ^ Merritt, Rick (Mar. 02, 2005). Intel preps HyperTransport competitor for Xeon, Itanium CPUs. techbuilder.org. Retrieved on 2007-03-31.
  11. ^ Intel Itanium Developer Manuals
  12. ^ Intel product announcement
  13. ^ Vance, Ashlee (June 1, 2006). HP grabs 90 per cent of 'industry standard' Itanic market. The Register. Retrieved on 2007-01-28.
  14. ^ Itanium Solutions Alliance
  15. ^ ISA press release
  16. ^ a b Shankland, Stephen (28 Feb 2005). Itanium dealt another blow. ZDNet.co.uk. Retrieved on 2007-03-24.
  17. ^ Intel Compiler press release
  18. ^ Intel Compilers
  19. ^ Gelato GCC Wiki
  20. ^ Documentation at GNU.org
  21. ^ ISA press release
  22. ^ Gelato Developing for Linux on Itanium
  23. ^ November 2006 Top500 list
  24. ^ Tera-10 at TOP500
  25. ^ a b Columbia at TOP500
  26. ^ Intel Montvale slated for Q4 2007 (November 14, 2006).
  27. ^ Goodwins, Rupert (26 Feb 2007). The Big Interview: Pat Gelsinger. ZDNet UK. Retrieved on 2007-03-19.
  28. ^ a b c d e f g h Mining Itanium. CNet News (December 7, 2005). Retrieved on 2007-03-19.
  29. ^ Dell to Integrate Merced. HPCWire (October 17, 1997). Retrieved on 2007-03-19.
  30. ^ IBM Previews Technology Blueprint For Netfinity Server Line. IBM (09 Sep 1998). Retrieved on 2007-03-19.
  31. ^ Titan NOW at TOP500
  32. ^ Thunder at TOP500
  33. ^ Morgan, Timothy (July 6, 2005). HP Ramps Up OpenVMS on Integrity Servers. ITJungle.com. Retrieved on 2007-03-29.
  34. ^ IBM server design drops Itanium support. Techrepublic.com (February 25, 2005). Retrieved on 2007-03-19.
  35. ^ Result submitted to SPEC on June 13, 2005 by Hitachi
  36. ^ Itanium Solutions Alliance Formed. Byte and Switch (September 26, 2005). Retrieved on 2007-03-24.
  37. ^ Shankland, Stephen (September 15, 2005). Dell shuttering Itanium server business. CNET News.com. Retrieved on 2007-03-19.
  38. ^ Shankland, Stephen (October 24, 2005). Intel pushes back Itanium chips, revamps Xeon. ZDNet News. Retrieved on 2007-03-17.
  39. ^ Bailey, Michelle, et.al. (February 2006). Customer Perceptions of the Future of Itanium. IDC. Retrieved on 2007-03-22.
  40. ^ Johnston, Stuart (February 23, 2006). IDC: Itanium 2 Poised for Takeoff. ENT News. Retrieved on 2007-03-21.
  41. ^ Shankland, Stephen (February 14, 2006). Analyst firm offers rosy view of Itanium. CNet News. Retrieved on 2007-03-20.
  42. ^ Preimesberger, Chris (July 19, 2006). Is 'Montecito' Intel's Second Chance for Itanium?. eWeek. Retrieved on 2007-03-23.

[edit] External links


Intel processors (italics indicate non-x86 processors)

4004 | 4040 | 8008 | 8080 | 8085 | 8086 | 8088 | iAPX 432 | 80186 | 80188 | 80286 | 80386 | 80486 | i860 | i960 | Pentium | Pentium Pro | Pentium II | Celeron | Pentium III | XScale | Pentium 4 | Pentium M | Pentium D | Pentium Extreme Edition | Pentium Dual Core | Pentium E | Xeon | Core | Core 2 | Itanium | Itanium 2

List of Intel microprocessors | List of Intel CPU slots and sockets


[[Category:Intel]] [[Category:Microprocessors]] [[Category:Instruction processing]] [[Category:Upcoming_chips]]

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