AHDL

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This article refers to AHDL as Altera Hardware Description Language. (AHDL also stands for Analog Hardware Description Language.)

AHDL is a proprietary Hardware Description Language (HDL) from Altera Corporation for programming their Complex Programmable Logic Devices (CPLD) and Field Programmable Gate Arrays (FPGA). Compiled with Altera's Quartus and Max+ series of compilers, this language has a C programming language-like syntax and similar operation to VHDL.

Introduction AHDL (Altera Hardware Description Language) was developed by Altera to provide their users a powerful way to develop designs for any Altera device. At that time HDL's (like VHDL and Verilog) where not default languages for CPLD and FPGA designers. By now VHDL and Verilog have become the industry standard languages for CPLD and FPGA design. However there are still a lot of designers with an impressive AHDL knowledge and even more realized AHDL projects. Translating your AHDL designs by hand is an error prone and time consuming activity. Most time will be lost in functional translation of your design as the implications of some AHDL constructs are easily overlooked.

Approach An in-house developed translator is the basis of the translation services. It has been developed with maintaining readability and design intend in mind. The translator translates the majority of AHDL constructs into VHDL or Verilog. Some language elements require manual post processing. The last step is the manual inspection of the translation results by an engineer. The translated VHDL or Verilog is synthesizable with all major synthesis tools.

Benefits • Design reuse of existing AHDL designs in VHDL or Verilog • Single design and test environment for your project • Automated translation prevents errors made during manual translation

Features • File based translation of AHDL modules into VHDL or Verilog • RTL based translation • Maintains design structure, comments and names • Automated conversion of illegal VHDL or Verilog identifiers • Translates expressions in their HDL counterpart • Supports defines and constant definitions • Supports wired 'and' and 'or' constructions

Limitations The following constructs are currently not supported • Multi dimensional arrays • USED function • In- or export of state machines through the design ports

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As a brief example, the following code snippet would implement an 8 bit up counter.

% a simple AHDL up counter, released to public domain 11/13/2006 %
% [block quotations achieved with percent sign] %
% like c, ahdl functions must be prototyped %

% PROTOTYPE:
 FUNCTION COUNTER (CLK)
        RETURNS (CNTOUT[7..0]); %

% function declaration, where inputs, outputs, and
bidirectional pins are declared %
% also like c, square brakets indicate an array %

SUBDESIGN COUNTER
(
        CLK             :INPUT;
        CNTOUT[7..0]    :OUTPUT;
)

% variables can be anything from flip-flops (as in this case),
tri-state buffers, state machines, to user defined functions %

VARIABLE
        TIMER[7..0]: DFF;

% as with all hardware description languages, think of this
 less as an algorithm and more as wiring nodes together %

BEGIN
        DEFAULTS

                TIMER[].prn = VCC; %  this takes care of d-ff resets %
                TIMER[].clrn = VCC;
        END DEFAULTS;

        TIMER[].d = TIMER[].q + H"1";
END;

More information on AHDL, as well as a freeware compiler* for windows, can be obtained from the Altera Corporation.

• Quartus II web edition