A20 line
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The A20 or addressing line 20 is one of the plethora of electrical lines that comprise the system bus of an x86 based computer system. The A20 line in particular is used to transmit the 21st bit on the address bus.
A microprocessor will typically have a number of addressing lines equal to the base-two logarithm of its physical addressing space. For example an Intel 80386 with its 4 GiB physical addressing space requires 32 lines, which are named A0 through A31. The lines are named after the number of the bit in the address they are transmitting. Thus, A0 will transmit the least significant bit, which is bit 0. A20 transmits bit 20 and will become active once addresses reach 1 MiB or 220. (It should be noted that in the case of the 80386 the A0 and A1 lines do not actually exist as such, as this processor addresses memory in 4 byte words, indicating through separate Byte Enable lines which of the 4 bytes are of interest for a given memory transfer.)
[edit] History
When IBM designed the IBM PC AT machine, they decided to use the new higher-performance Intel 80286 microprocessor, which was not entirely compatible with the previous Intel 8088 and Intel 8086 microprocessors when in real mode. Previous x86 microprocessors did not have bus lines for A20 through A31; therefore, addresses above the first megabyte would appear to the processors to wrap externally. The 80286 could address up to 16 MB of system memory, thus removing the ability for memory addresses to wrap around.
Many real mode programs took and still take advantage of this, thus making it a common trick to access the first 64 KB of memory without changing the processor's segment registers. In order to remain compatible with these programs, IBM decided to fix the problem themselves, at the motherboard level.
This was accomplished by inserting a logic gate on the A20 line between the processor and system bus, which logically got named Gate-A20. Gate-A20 can be enabled or disabled by software to allow or prevent the address bus from receiving a signal from A20. It is set to non-passing for the execution of older programs which rely on the wrap-around. At boot time, the BIOS first enables Gate-A20 when counting and testing all of the system's memory, and disables it before transferring control to the operating system.
Originally, the logic gate was a gate connected to the Intel 8042 keyboard controller. Controlling it was a relatively slow process. Other methods have since been added to allow for more efficient multitasking of programs which require this wrap-around with programs that access all of the system's memory.
It should be noted that disconnecting A20 would not wrap all memory accesses above 1 MB, just those in the 1 MB-2 MB, 3 MB-4 MB, 5 MB-6 MB, etc. ranges. Real mode software only cared about the area slightly above 1 MB, so Gate-A20 was enough.
Over the time, the A20 line expression became confused with Gate-A20 among less technically savvy audiences.
Enabling the Gate-A20 line is one of the first steps a protected mode x86 operating system does in the bootup process, often before control has been passed onto the kernel from the bootstrap (in the case of Linux, for example).
Virtual 8086 mode, introduced with the Intel 80386, allows the A20 wrap-around to be simulated by using the virtual memory facilities of the processor: physical memory may be mapped to multiple virtual addresses thus allowing the memory mapped at first megabyte of virtual memory may be mapped again in the second megabyte of virtual memory. The operating system may intercept changes to Gate A20 and make corresponding changes to the virtual memory address space, which also makes irrelevant the efficiency of Gate-A20 toggling.
The Intel 80486 added a special pin named A20M#, which when asserted low forces bit 20 of the physical address to be zero for all on-chip cache or external memory accesses. This enhancement is mostly significant for mainboard manufacturers, because it makes parts of the external Gate A20 circuitry unnecessary. Software still needs to manipulate the gate and must still deal with external peripherals (the chipset) for that.
