65 nanometer

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CMOS manufacturing
processes

10 µm
3 µm
1.5 µm
1 µm
800 nm (0.80 µm)
600 nm (0.60 µm)
350 nm (0.35 µm)
250 nm (0.25 µm)
180 nm (0.18 µm)
130 nm (0.13 µm)
90 nm
65 nm
45 nm
32 nm
22 nm
16 nm

The 65 nanometer (65 nm) process is (as of 2007) the most advanced lithographic node used in volume CMOS semiconductor fabrication. Minimum feature sizes can reach as low as 35 nm on a "65 nm" process. For reference, cellular ribosomes are about 20 nm end-to-end. A crystal of bulk silicon has a lattice constant of .543 nm, so such transistors are on the order of 100 atoms across. Intel, AMD, IBM, UMC, and TSMC are currently producing 65 nm chips. Companies planning 65 nm production include Texas Instruments, Cypress Semiconductor and Motorola.

While average feature sizes are 65 nm, the wavelengths of light used are 193 nm and 248 nm. Fabrication of sub-wavelength features is possible when various effects are taken into account. Manufacturers must compete to invent new image processing and optical technologies, such as phase-shifting masks, to counter the tendency toward image blurring and distortion in the sub-wavelength regime.

Gate thickness, another important dimension, is reduced to as little as 1.2 nm (Intel). Only a few atoms insulate "switch" part of the transistor, causing charge to flow through it. This undesired effect, leakage, is caused by quantum tunneling. The new chemistry of high-k gate dielectrics must be combined with existing techniques including substrate bias and multiple threshold voltages to prevent leakage from prohibitively consuming power.

IEDM papers from Intel in 2002, 2004 and 2005 indicate that the minimum feature pitch did not change much (220 nm to 210 nm) going from 90 nm to 65 nm node, even for the low power process. This suggests that scaling down the distance between microprocessor transistors is slowing down dramatically, but chip size can be made smaller by crowding a larger fraction of transistors at the minimum distance.