45 nanometer

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CMOS manufacturing
processes

10 µm
3 µm
1.5 µm
1 µm
800 nm (0.80 µm)
600 nm (0.60 µm)
350 nm (0.35 µm)
250 nm (0.25 µm)
180 nm (0.18 µm)
130 nm (0.13 µm)
90 nm
65 nm
45 nm
32 nm
22 nm
16 nm

The 45 nanometer (45 nm) process is the next milestone (to be commercially viable in mid 2007 to early 2008) in CMOS fabrication. Intel is targeting 45 nm production in late 2007, AMD in late 2007 to Q2 2008, and Intel, IBM, Infineon, Samsung, Chartered Semiconductor, Toshiba, and Sony have completed a common 45 nm process.

Per ITRS, the 45 nm technology node should have significantly tighter specs than the current 65 nm node. '45 nm' itself should refer to the average half-pitch of a memory cell manufactured at that technology level.

While average feature sizes are less than 65 nm, the wavelength of light used is actually 193 nm. A variety of techniques, such as larger lenses, are used to make sub-wavelength features. Double patterning may also be introduced to assist in shrinking distances between features, especially if dry lithography is used.

Intel stated in 2003 that high-k gate dielectrics may be introduced at the 45 nm node to reduce gate leakage current. Chipmakers have since then voiced concerns about introducing these new materials into the gate stack. As of 2007, however, both IBM and Intel have announced that they have high-k and metal gate solutions.

[edit] Technology demos

In 2004, TSMC demonstrated a 0.296 square micrometer 45 nm SRAM cell. Such a prototype is useful for characterizing future technology, but cannot be mass produced as it is manufactured using fundamentally different techniques.

In January 2006, Intel demonstrated a 0.346 square micrometers 45 nm node SRAM cell.

In April 2006, AMD demonstrated a 0.370 square micrometer 45 nm SRAM cell.

In June 2006, Texas Instruments debuted a 0.24 square micrometer 45 nm SRAM cell, with the help of immersion lithography.

In November 2006, UMC announced that it had developed a 45 nm SRAM chip with a cell size of less than 0.25 square micrometer using immersion lithography and low-k dielectrics.

The successors to 45 nm technology will be 32 nm, 22 nm, and then 16 nm technology per ITRS.