32-bit x86 assembly programming
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This article applies when the default operand size is 32-bit, which is only possible on 386s+ in protected mode.
[edit] Application registers
In protected mode, there are 8 32-bit general-purpose registers for use:
- data registers
- EAX, the accumulator
- EBX, the base register
- ECX, the counter register
- EDX, the data register
- address registers
- ESI, the source register
- EDI, the destination register
- ESP, the stack pointer register
- EBP, the stack base pointer register
In addition there are non-application registers available, which change the state of the processor:
- control registers
- CR0
- CR1
- CR2
- CR3
- CR4
- debug registers
- DR0
- DR1
- DR2
- DR3
- DR6
- DR7
- test registers
- TR4
- TR5
- TR6
- TR7
- descriptor registers
- GDTR, the global descriptor table register
- LDTR, the local descriptor table register
- IDTR, the interrupt descriptor table register
- task register
- TR
All of them can be used both for segmented addressing of memory and for holding data. Some of these registers are however better to use for certain operations than others. This is because mnemonics using certain registers could be translated into shorter opcodes than if they used other registers.
The lower 16 bits of each 32 bit register can be addressed separately and like a register in its own right, and the low 16 bits of the first four registers (EAX, EBX, ECX, EDX) can be further broken up into two eight-bit registers. The 16 bits of data in these first four 16 bit registers can be addressed 8 bits at a time: the upper eight and the lower eight bits, and can be treated as registers in their own right.
If we take the EAX register, this register contains 32 bits and the lower 16 bits can be addressed by the AX register. The upper 8 bits of the AX register can be addressed by the AH register and the lower 8 bits of the AX register can be addressed by the AL register.
For example, if ECX initially contains the number 0x3A3F901D and CH changes to 0x44, then ECX will also change to contain 0x3A3F441D.
There is also a 32-bit wide flags register, named EFLAGS, which contain the processor state. Each flag is one bit - and thus set 0 or 1, also called set, high, and unset or low. Important flags in the EFLAGS register are: carry (bit 0), zero (bit 6), sign flag (bit 7) and overflow (bit 11).
Flags are notably used in the x86 architecture for comparisons. A comparison is made between two registers, for example, and in comparison of their difference a flag is raised. A jump instruction then checks the respective flag and jumps if the flag has been raised: for example
cmp eax, ebx
jne do_something
first compares the EAX and EBX registers, and if they are unequal, the code branches off to the do_something label.
There is also a 32-bit instruction pointer, named EIP. The EIP register points to where in the program the processor is currently executing its code. The EIP register cannot be accessed by the programmer directly. Instead, a sequence like the following can be done to retrieve the address of next_line into EAX:
call next_line
next_line:
pop eax
This works even in position-independent code because call takes an EIP-relative immediate operand. To write to EIP is simple:
jmp eax
[edit] Segmentation
For 32-bit segmented code, the info in the 16-bit x86 assembly programming that applies to protected mode applies, except that offsets are 32-bit and far pointers are 48-bit, called a FWORD in assembly language.
