16 nanometer

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CMOS manufacturing
processes

10 µm
3 µm
1.5 µm
1 µm
800 nm (0.80 µm)
600 nm (0.60 µm)
350 nm (0.35 µm)
250 nm (0.25 µm)
180 nm (0.18 µm)
130 nm (0.13 µm)
90 nm
65 nm
45 nm
32 nm
22 nm
16 nm

The 16 nanometer (16 nm) node is the technology node following 22 nm node. By conservative estimates this technology is expected to be reached by semiconductor companies in the 2018 timeframe.^[1] At that time, the typical half-pitch for a memory cell would be around 16 nm. The exact naming of this technology node comes from the International Technology Roadmap for Semiconductors (ITRS). However, if the industry continues to follow a two year cycle the 16 nm node will be reached in 2013.^{[citation needed]}

At this point, very few 16 nm features are capable of being produced using reliable processes in mass quantity, with some notable attempts like carbon nanotubes. Even in these cases, the variation within any sample population is quite large and the compatibility of such exotic processes and materials with current mainstream ones present further issues.

Toshiba recently demonstrated 15 nm gate length and 10 nm fin width using a sidewall spacer process.

For comparison an atom has a diameter of 0.1 to 0.7 nanometers.

Preceded by 22 nm	CMOS manufacturing processes	Succeeded by various predictions

[edit] References

^ Intel scientists find wall for Moore's Law

A. Kaneko et. al., "Sidewall Transfer Process and Selective Gate Sidewall Spacer Formation Technology for Sub-15nm FinFET with Elevated Source/Drain Extension," IEDM 2005.