Zero Instruction Set Computer

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In computer science, ZISC stands for Zero Instruction Set Computer, which refers to a chip technology based on pure pattern matching and absence of (micro-)instructions in the classical sense.

The ZISC acronym alludes to the previously developed RISC (Reduced Instruction Set Computer) technology.

ZISC is a technology based on ideas from artificial neural networks. The concept was invented by Guy Paillet and it was jointly developed by Guy Paillet and Dr. Pascal Tannhof with IBM in Paris. The first generation of ZISC chip contains 36 independent cells that can be thought of as neurons or parallel processors. Each of these can compare an input vector of up to 64 bytes with a similar vector stored in the cells memory: if the input vector matches the vector in the cells memory, the cell "fires". The output signal contains the number of the cell that had a match or "no matches occurred" indicator.

The parallelism is the key to the speed of ZISC systems, which eliminate the step of serial loading and comparing the pattern for each location. Another key factor is ZISC's scalability. A ZISC network can be expanded by adding more ZISC devices without suffering a decrease in recognition speed - networks with 10,000 or more cells might become common. Today's ZISC chip contains 78 neurons per chip and can find a match among 1,000,000 patterns in one second operating at less than 50 MHz. Future generation will be 1,000 neurons or more.

Practical uses of ZISC technology focus on pattern recognition, information retrieval (data mining), security and similar tasks.