UltraSPARC T2

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Sun Microsystems' UltraSPARC T2 microprocessor, is a multithreading, multi-core CPU. The UltraSPARC T2's predecessor is the UltraSPARC T1. The chip is sometimes referred to by the codename Niagara II. It is expected to be included in new systems from Sun in the second half of 2007.^[1]

1 New Features
2 Core Pipeline
3 Tape-Out
4 References
5 See also
6 External link

[edit] New Features

The T2 is a derivative of the UltraSPARC series of microprocessors. The processor, manufactured in 65 nm, is available with eight CPU cores, and each core is able to handle eight threads concurrently. Thus the processor is capable of processing up to 64 concurrent threads. Other new features include:

Speed bump for each thread, increased to 1.4 GHz from 1.2 GHz
one PCI Express port (x8 1.0)
two 10 Gigabit Ethernet ports with packet classification and filtering
the L2 cache size increased to 4 MB (8-banks, 16-way associative)
1 floating point unit per core, up from just 1 FPU per CPU
eight encryption engines (instead of just one in T1)
four dual-channel FBDIMM memory controllers

[edit] Core Pipeline

There are 8 stages for integer operations, instead of 6 in the T1.

Processor	Stages
T1's pipeline	Fetch		Thread Selection	Decode	Execute	Memory Access		Writeback
T2's pipeline	Fetch	Cache	Thread Selection	Decode	Execute	Memory Access	Bypass	Writeback

[edit] Tape-Out

On April 12, 2006, Sun announced the tape-out completion of the T2. It also disclosed that under the same power envelope, the T2 will deliver twice the performance of the T1 when running transactional workload.^[1]