UltraSPARC T1

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Sun Microsystems' UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename "Niagara" , is a multithreading, multicore CPU. Designed to lower the energy consumption of server computers, the CPU uses typically 72 W of power at 1.2 GHz.

The T1 is a new-from-the-ground-up SPARC microprocessor implementation that conforms to the UltraSPARC Architecture 2005 specification and executes the full SPARC V9 instruction set. Sun has produced two previous multicore processors UltraSPARC IV and UltraSPARC IV+, but UltraSPARC T1 is its first microprocessor that is both multicore and multithreaded. The processor is available with four, six or eight CPU cores, each core able to handle four threads concurrently. Thus the processor is capable of processing up to 32 threads concurrently.

Similar to how high-end Sun SMP systems work, the UltraSPARC T1 can be partitioned. Thus, several cores can be partitioned for running a single or group of processes and/or threads, whilst the other cores deal with the rest of the processes on the system.

Contents 1 Cores 2 Target market 3 "Rock" 4 Niagara 2 5 Open Design 6 External links

[edit] Cores

The UltraSPARC T1 was designed from scratch as a multi-threaded, special-purpose processor, and thus introduces a whole new architecture for obtaining high performance. Rather than try to make each core as intelligent and optimized as they can, Sun's goal was to run as many concurrent threads as possible, and maximize utilization of each core's pipeline.

The T1's cores are less complex than those of current high end processors in order to allow 8 cores to fit on the same die. The cores do not feature out-of-order execution, or a sizable amount of cache. Single-thread processors depend heavily on large caches for their performance because cache misses result in a wait while the data is fetched from main memory. By making the cache larger the probability of a cache miss is reduced, but the impact of a miss is still the same.

The T1 cores largely side-step the issue of cache misses by multithreading. When a cache miss occurs, the core switches to another thread (assuming one is available) while the data is fetched into cache in the background. This may make each thread slower, but the overall throughput (and utilization) of each core is much higher. It also means that much of the impact of cache misses is removed, and the T1 can maintain high throughput with a smaller amount of cache. The cache no longer needs to be large enough to hold all or most of the "working set", just the recent cache misses of each thread.

Benchmarks demonstrate this approach has worked very well on commercial (integer), multithreaded workloads such as Java application servers, Enterprise Resource Planning (ERP) application servers, and web servers. These benchmarks suggest each core in the UltraSPARC T1 is more powerful than the circa 2001, single-core, single-threaded UltraSPARC III, and at a chip to chip comparison, significantly outperforms other processors on multithreaded integer workloads.

At the time of its release in December of 2005, a single chip, eight core, 32-thread, 1.2 GHz UltraSPARC T1 server performed similarly to a two-socket, four-core, eight-thread, 1.9 GHz IBM POWER5 server, performed similarly to a four socket, eight-core, sixteen-thread 3.0 GHz Intel Xeon "Paxville MP" server, and exceeded the performance of a four socket, four-core, four-thead 1.6 GHz Intel Itanium server. Arguably, this made the UltraSPARC T1 the world's most powerful general-purpose commercial server processor, when considering multithreaded commercial workloads.

[edit] Target market

The microprocessor is unique in its abilities, and as such is targeted at a particular market. Rather than being used for high-end number-crunching and ultra-high performance applications, the chip will be targeted at network-facing high-demand servers, such as high-traffic web servers, and mid-tier Java, ERP, and CRM application servers, which often utilize a large number of separate threads. One of the limitations of the UltraSPARC T1 design is that a single floating point unit is shared between all 8 cores, making the T1 unsuitable for applications performing a lot of floating point mathematics. However, since the processor's intended market does not typically make much use of floating-point operations, Sun does not expect this to be a problem.

In addition to web and application tier processing, the UltraSPARC T1 may be well suited for smaller database application which have a large user count. This is an example of a customer comparing a MySQL application running on an UltraSPARC T1 server to an AMD Opteron server.

[edit] "Rock"

The UltraSPARC T1 is designed for single CPU systems only and is not capable of SMP. Future Sun CMT UltraSPARC processors, such as Rock, will support multiple chip server architectures. The Rock processor targets traditional data facing workloads such as databases. As such, it is seen as the logical follow-on to Sun's SMP processors such as UltraSPARC III.

Rock also targets floating point workloads, unlike UltraSPARC T1. Sun has publicly disclosed a feature in the Rock processor called "Hardware Scout", which uses multithreaded hardware to perform prefetching.

Rock is not a successor to UltraSPARC T1. Sun has publicly disclosed plans for a UltraSPARC T2 processor which will target the same network facing workloads as UltraSPARC T1.

[edit] Niagara 2

The follow-on to the UltraSPARC T1, the Niagara2 processor (also referred to as the UltraSPARC T2) will support eight threads per core, and each core will have its own FPU.

[edit] Open Design

On March 21, 2006, Sun made the UltraSPARC T1 processor design available under the GNU General Public License via the OpenSPARC project. The published information includes:

• Verilog source code of the UltraSPARC T1 design;
• Verification suite and simulation models;
• ISA specification (UltraSPARC Architecture 2005);
• The Solaris 10 OS simulation images.

[edit] External links

• Sun Microsystems' official UltraSPARC T1 Processor information
• Sun's OpenSPARC homepage
• OpenSPARC T1 Project home
• Sun Intros Eight-Core Processor – By Jessica Davis, Electronic News, 14 Nov 2005
• Sun’s Big Splash by Linda Geppert, in IEEE Spectrum, January 2005
• Niagara, a 32-way Multithreaded Sparc Processor by Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun, in IEEE Micro, March-April 2005