Tomasulo algorithm

From Wikipedia, the free encyclopedia

1 Introduction/Overview
2 Implementation Concepts
3 Instruction Lifecycle
4 Example
5 See also
6 References

[edit] Introduction/Overview

The Tomasulo algorithm is a hardware algorithm developed in 1967 by Robert Tomasulo from IBM. It allows sequential instructions that would normally be stalled due to certain dependencies to execute non-sequentially (out-of-order execution). It was first implemented for the IBM360/91’s floating point unit.

This algorithm differs from scoreboarding in that it utilizes register renaming. Where scoreboarding resolves Write-after-Write (WAW) and Write-after-Read (WAR) hazards by stalling, register renaming allows the continual issuing of instructions. The Tomasulo algorithm also uses a common data bus (CDB) on which computed values are broadcast to all the reservation stations that may need it. This allows for improved parallel execution of instructions which may otherwise stall under the use of scoreboarding.

Robert Tomasulo received the Eckert-Mauchly Award in 1997 for this algorithm.

[edit] Implementation Concepts

The following are the concepts necessary to the implementation of Tomasulo's Algorithm.

Instructions are issued sequentially so that the effects of a sequence of instructions, such as exceptions raised, occur in the same order as they would in a non-pipelined processor, regardless of the fact that they are being executed non-sequentially.

All general-purpose and reservation station registers hold either real or virtual values. If a real value is unavailable to a destination register during the issue stage, a virtual value is initially used. The functional unit that is computing the real value is assigned as the virtual value. The virtual register values are converted to real values as soon as the designated functional unit completes its computation.

Functional units use reservation stations with multiple slots. Each slot holds information needed to execute a single instruction, including the operation and the operands. The functional unit begins processing when it is free and when all source operands needed for an instruction are real.

[edit] Instruction Lifecycle

The three stages listed below are the stages through which each instruction passes from the time it is issued to the time its execution is complete.

[edit] Stage 1: Issue

In the Issue stage, instructions are issued for execution if all operands and reservation stations are ready or else they are stalled. Registers are renamed in this step, eliminating WAR and WAW hazards.

Retrieve the next instruction from the head of the instruction queue
If the instruction operands are currently in the registers
- If there is a matching empty reservation station (functional unit is available)
  - Issue the instruction
- Else, if there is not an empty reservation station
  - Stall the instruction until a station or buffer is free
Else, if the operands are not in the registers
- Use virtual values to track of the functional units that will produce the operands

[edit] Stage 2: Execute

In the Execute stage, the instruction operations are carried out. Instructions are delayed in this step until all of their operands available, eliminating RAW hazards. Program order is maintained through effective address calculation to prevent hazards through memory.

If one or more of the operands is not yet available
- Monitor the common data bus (CDB) while waiting for it to be computed
- Place operands into corresponding reservation station when they become available
When all operands are available
- If the instruction is a load or store
  - Compute the effective address when the base register is available
  - Place the effective address in the load or store buffer
  - If the instruction is a load
    - Execute as soon as the memory unit is available
  - Else, if the instruction is a store
    - Wait for the value to be stored before sending it to the memory unit
- Else, the instruction is an ALU operation
  - Execute the instruction at the corresponding functional unit

[edit] Stage 3: Write Result

In the Write Result stage, ALU operations results are written back to registers and store operations are written back to memory.

If the instruction was an ALU operation
- When the result is available,
  - Write it on the CDB and from there into the registers and any reservation stations waiting for this result
Else, if the instruction was a store
- Write the data to memory during this step

[edit] Example

The following is an example of the reservation station status when all of the instructions have issued, but only the first load instruction has completed and written its result to the CDB.

1. L.D F6, 34(R2)

2. L.D F2, 45(R3)

3. MUL.D F0, F2, F4

4. SUB.D F8, F2, F6

5. DIV.D F10, F0, F6

6. ADD.D F6, F8, F2