Talk:SpeedStep
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Why they're is a "f" here? I think it's a mistake but I want to be sure before making any modifications.
For example, a Pentium M processor marketed at 1.5 GHz can run at any speed between 600 MHz and 1.f5 GHz, at 100 MHz increments, using SpeedStep III.
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[edit] Any Mac OS X specific info?
- I see Linux and Windows are mentioned in the OS support section, but nothing about Mac OS X.
- Could you please elaborate? Maybe you should be the one to add it? I don't know anything about speedstep support in Mac OS X, otherwise I would be glad to add it. -Ricky28269
[edit] EIST?
/Speedstep in desktops? Supported CPUs?
[edit] confusing or unclear
I have no good sources, but I do not want this article to be written like SpeedStep was the first measure to reduce power consumption of CPUs.--Arnero 19:10, 20 July 2006 (UTC)
[edit] Predecessors
This section has totally lame contents, so I will remove it. The idea of having such a section if fine. But someone would have to write it with useful contents. 69.87.202.196 15:00, 7 December 2006 (UTC)
Predecessors This article or section may be confusing or unclear for some readers. Please improve the article or discuss this issue on the talk page. This article has been tagged since December 2006.
1980
The halt command stops the CPU. Since it is fabricated using CMOS technology, no energy is used for the CPU logic.
2003
Modern mainboards have voltage regulator modules (which are a kind of switch-mode power supplies) integrated into the mainboards themselves, which can be programmed by the mainboards BIOS, to accommodate the specific CPU requirements. Lower voltage means longer clock cycle and less energy per cycle.
2005
The halt command also stops the clock.[5]
[edit] Implementation
This section is so weird and garbled that I am going to take it out. 69.87.202.196 15:08, 7 December 2006 (UTC)
- Implementation *
Currently the clock speed and core voltage is changed explicitly by the OS. At least the maximum voltage will always be set by the OS, so that small bursts of CPU activity in typical office applications do not eat up too much energy on mobile applications.
A fast reaction to sporadic external events would need a low level, zero overhead scheme: The halt command stops the voltage regulator modules. When an interrupt restarts the CPU it first have to be "charged" (takes about 2 µs). With only short bursts of CPU activity most of the activity takes place at low voltage. The trend goes to 100 MHz switching.[1]
A close look to the voltage regulation reveals that a capacitor is charged by MOSFET switched transformers and discharge by various parts of the CPU all producing noise. A bigger capacitor reduces the noise but also the speed the voltage can be actively changed. In principle a CPU could use a ring oscillator made of the same transistors as the core logic to adapt each cycle length to the current voltage. Because the interface section of the CPU runs at a different voltage and clock speed FIFOs and level shifters are needed. When reading the FIFO it has to be checked if the value at the read position is already valid. Because this validity bit can change while reading out a comparator is needed to generate valid logic levels. Because the comparator is so slow that it delivers a results with about 20 cycles latency, the results are predicted digitally and conservatively (assuming a maximum allowed voltage drop). Even slower clock rate changes oblige mainboards to go long ways to ensure ripple free voltage and soft transients.
