Talk:SPARC
From Wikipedia, the free encyclopedia
Sparc64 is not the T1 (Niagara) as implied by the article. —The preceding unsigned comment was added by 12.35.167.242 (talk • contribs) 11:26, 5 May 2006 (UTC).
- Where does the current version of the article (after my changes to make the article no longer refer to SPARC64 as "the latest multi-core processor of Sun") imply that? Guy Harris 18:59, 5 May 2006 (UTC)
-
- Well, it still said "It has eight cores with a clock speed of 1.2 GHz per core. Each core is capable of running four threads simultaneously." That's true of the UltraSPARC T1, but not of any SPARC64 processor, as far as I can tell. I've removed that sentence for now. --StuartBrady 23:14, 5 May 2006 (UTC)
Inaccurate, false, incomplete.
1. The article doesn't distinguish between an instruction set architecture and a particular implementation of the architecture. SPARC is an ISA specification. and UltraSPARCs are particular implementations. You can design and manufacture SPARC compatible processors, but you can't do that with x86. That's why SPARC is called open.
- Please explain. AMD makes x86 compatible chips. What is it you're saying?
-
- I think it means that with SPARC there's no need for sneakiness, no reverse-engineering, no Silicon Valley virginity test. - Robert X. Cringely
2. It's ridiculous to imply that the original design favored register window *instead of* pipelining since the first SPARC was pipelined. Ever wondered why the delay slot was invented in the first place ? To fill the pipeline bubble after the branch in the early RISC designs.
3. UltraSPARC series are not a "standard" but just particular implementations.
4. In v9, there are 32 double precision (64bit) floating point registers, and half of them (16) can be used as 32 single precision floating point registers. These 32 double precision registers can be used as 16 quad precision registers also.
5. There's 8 global registers which are always available but no mention of it - the article implies there's only 24 general purpose registers available.
6. If a delay slot makes coding awkward, try hand-coding IA-64.
7. The article was apparently written by some open source zealot, but obviously the zealot had no clue on processors like Leon which is a particular implementation of SPARC and is open source (as the core design VHDL is under GPL). Have you ever seen an x86 design under GPL ? No, since that's impossible unless Intel allows. That's why SPARC is an open architecture.
I'll try to write a fair and accurate article on SPARC if I have some time, but if there's anybody with enough time to do so, take a look at http://www3.sk.sympatico.ca/jbayko/cpu.html before writing anything to get some clue.
http://www3.sk.sympatico.ca/jbayko/cpu.html dead link
What are you getting at in #6 ?
Is Solaris really "designed for SPARC"? Or what did the old 68000-based Sun3 machines run?
- sun1, sun2, sun3, sun4, sun3x, sun4c and early sun4m machines shipped with SunOS witch was based on BSD UNIX.
link active as of 20050812: http://www.sasktelwebsite.net/jbayko/cpu.html
There's no mention of Ross Technology, which made the HyperSPARC processors and closed in 1998 [1]. However, I'm unclear on whether they would have actually licensed SPARC from SPARC International, so I'm not sure how to add this. StuartBrady 15:37, 12 January 2006 (UTC)
- Ross were spun off from Cypress, who were the builders of the first full-custom SPARC processors (the 7C601, or whatever the number was), and who were "licensed" for SPARC before SI existed; presumably they inherited whatever "license" they had from Cypress. Guy Harris 18:37, 12 January 2006 (UTC)
The article barely mentions SPARC V7 revision, in which the ERC32 processor is based on.
Contents |
[edit] Tagged Instructions
Currently, the last paragraph under SPARC#Features is slightly incorrect.
- Tagged add and subtract instructions perform adds and subtracts on values assuming that the bottom two bits do not participate in the computation. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.
The tagged instructions were added for the sake of Smalltalk, Lisp and other dynamically-typed languages, but Urs Hölzle and David Ungar report little benefit, at least for the Self programming language (see Do object-oriented languages need special hardware support?, ECOOP 1995). So I suggest changing the second sentence to (say)
- They were added for the sake of dynamically-typed languages such as Smalltalk, Lisp and ML that might use a tagged integer format.
If anyone can point to a system which does gain some real benefit from those instructions, I'd love to know about it. (When I first read about TADDcc and TSUBcc, I thought they were a wonderful idea. When I read that paper I was quite suprised. It would greatly please me to find about that TADDcc & TSUBcc are useful after all.)
- —Chris Chittleborough 14:28, 20 March 2006 (UTC)
[edit] Table of Processors
The table which shows details about the SPACR Processor is quite unreadable, is there any tutorial which tell me to add another headings in the row so that it could be quite readable ?
[edit] Multi-core/multi-thread SPARC64
The slide show from October 2005 at http://primeserver.fujitsu.com/primepower/event/report/pf-2005/pdf/mpf2005scr.pdf says that SPARC64 VI is intended to be dual-core with each core supporting two "strands". It doesn't indicate that any current SPARC64 is either multi-core or multi-threaded. Guy Harris 21:18, 5 May 2006 (UTC)
[edit] Superscalar/In-order, etc ?
The article doesn't even mention wether versions of Sparc are superscalar, our of order, in order, how wide, etc. I'd say that this is at least as important and interesting (if not more) as cache size.
