SPARC
From Wikipedia, the free encyclopedia
- Not to be confused with Social and Public Art Resource Center.
SPARC (Scalable Processor ARChitecture) is a RISC microprocessor instruction set architecture originally designed in 1985 by Sun Microsystems. SPARC is a registered trademark of SPARC International, Inc., an organization established in 1989 to promote the SPARC and to provide conformance testing. SPARC International was intended to "open" the SPARC architecture to make a larger ecosystem for the design, which has been licensed to several manufacturers, including Texas Instruments, Cypress Semiconductor, and Fujitsu. As a result of SPARC International, the SPARC architecture is fully open and non-proprietary.
In fact, there are two fully open source implementations available. The source code (written in VHDL) of a 32-bit, single-thread SPARC Version 8 implementation called LEON is available under the LGPL. A 64-bit, 32-thread implementation that conforms to the UltraSPARC Architecture 2005 and to SPARC Version 9, called OpenSPARC T1, is also available under an open source license. The OpenSPARC T1 implementation is written in Verilog.
Implementations of the SPARC architecture were initially designed and used for workstations, and then used for larger SMP servers produced by Sun Microsystems and Fujitsu, among others. SPARC machines generally use Sun's Solaris Operating System (designed for SPARC), but other operating systems such as NEXTSTEP, RTEMS, FreeBSD, OpenBSD, NetBSD, and Linux are also used on SPARC-based systems.
There have been several revisions of the architecture. SPARC Version 8 (V8), considered the standard 32-bit SPARC architecture definition, was released in approx 1989. SPARC Version 9, the 64-bit SPARC architecture, was released by SPARC International in 1994. In early 2006, Sun released an extended architecture specification, UltraSPARC Architecture 2005. UltraSPARC Architecture 2005 includes not only the nonprivileged and most of the privileged portions of SPARC V9, but also all the architectural extensions (such as CMT, hyperprivileged, VIS 1, and VIS 2) present in Sun's UltraSPARC processors starting with the UltraSPARC T1 implementation.
The 32-bit SPARC V8 architecture is a purely big-endian architecture. The 64-bit SPARC V9 architecture utilizes big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at the application instruction (load/store) level or at the memory page level (via an MMU setting). The latter is often used for accessing data from inherently little-endian devices, such as those on PCI buses.
As of December 2005 Sun announced their UltraSPARC T1 design would be open sourced, and in March 2006 the full source code became available (see OpenSPARC).
Contents |
[edit] Features
The SPARC architecture was heavily influenced by the earlier designs of the RISC I & II from the University of California, Berkeley. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per clock cycle. This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot.
The SPARC processor usually contains as many as 128 general purpose registers. At any point, only 32 of them are immediately visible to software - 8 are global registers (one of which, g0, is hard-wired to zero, so only 7 of them are usable as registers) and the other 24 are from the stack of registers. These 24 registers form what is called a register window, and at function call/return, this window is moved up and down the register stack. Each window has 8 local registers and shares 8 registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for retaining local values across function calls. The "Scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (nonprivileged) instruction set. One of the architectural parameters that can scale is the number of implemented register windows; the specification allows from 3 to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum call stack efficiency, or to implement only 3 to reduce context switching time, or to implement some number between them. Other architectures that include similar register windows include Intel i960, IA-64, and AMD 29000.
In SPARC version 8 (1987), the floating point register file has 16 double precision registers. Each of them can be used as two single precision registers, providing a total of 32 single precision registers. An odd-even number pair of double precision registers can be used as a quad precision register, thus allowing 8 quad precision registers. SPARC Version 9 (1995) added 16 more double precision registers (which can also be accessed as 8 quad precision registers), but these additional registers can not be accessed as single precision registers.
Tagged add and subtract instructions perform adds and subtracts on values assuming that the bottom two bits do not participate in the computation. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.
[edit] History
The architecture has gone through a few revisions. It gained hardware multiply and divide functionality in version 8. The most substantial upgrade resulted in version 9, which is a 64-bit (addressing and data) SPARC specification.
A Sun-specific architecture specification, UltraSPARC Architecture 2005, added specification of additional instructions, registers, and hyperprivileged mode — all of which had became standard in UltraSPARC processors starting with the UltraSPARC T1 8-core, 32-thread implementation. UltraSPARC Architecture 2005 includes Sun's standard extensions and remains compliant with the full SPARC V9 Level 1 specification. The architecture has provided continuous application binary compatibility from the first SPARC V7 implementation in 1987 into the Sun UltraSPARC Architecture implementations.
Sun open-sourced the UltraSPARC T1 implementation in December 2005; see OpenSPARC.
Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, so as to be used as reference systems for SPEC CPU95 and CPU2000 benchmarks.
The 296 MHz UltraSPARC-II version is the reference system for the SPEC CPU2006 benchmark.
| Model | Frequency [MHz] |
Architecture Version |
Year | Threads Per Core × Cores = Total Threads |
Process [µm] |
Transistors [millions] |
Die size [mm²] |
IO Pins | Power [W] |
Voltage [V] |
L1 Dcache [k] |
L1 Icache [k] |
L2 Cache [k] |
L3 Cache [k] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| microSPARC I | 40–50 | V8 | 1992 | 1×1=1 | 0.8 | 0.8 | 225? | 288 | 2.5 | 5 | 2 | 4 | none | none |
| SuperSPARC I | 33–60 | V8 | 1992 | 1×1=1 | 0.8 | 3.1 | -- | 293 | 14.3 | 5 | 16 | 20 | 0-2048 | none |
| hyperSPARC A | 40–90 | V8 | 1993 | 1×1=1 | 0.5 | 1.5 | -- | -- | -- | 5? | 0 | 8 | 128-256 | none |
| microSPARC II | 60–125 | V8 | 1994 | 1×1=1 | 0.5 | 2.3 | 233 | 321 | 5 | 3.3 | 8 | 16 | none | none |
| hyperSPARC B | 90–125 | V8 | 1994 | 1×1=1 | 0.4 | 1.5 | -- | -- | -- | 3.3 | 0 | 8 | 128-256 | none |
| SuperSPARC II | 75–90 | V8 | 1994 | 1×1=1 | 0.8 | 3.1 | 299 | -- | 16 | -- | 16 | 20 | 1024-2048 | none |
| hyperSPARC C | 125–166 | V8 | 1995 | 1×1=1 | 0.35 | 1.5 | -- | -- | -- | 3.3 | 0 | 8 | 512-1024 | none |
| TurboSPARC | 160–180 | V8 | 1995 | 1×1=1 | 0.35 | 3.0 | 132 | 416 | 7 | 3.5 | 16 | 16 | 512 | none |
| UltraSPARC I (Spitfire) | 143–167 | V9 | 1995 | 1×1=1 | 0.47 | 5.2 | 315 | 521 | 30 @167 MHz | 3.3 | 16 | 16 | 512-1024 | none |
| UltraSPARC I (Hornet) | 200 | V9 | 1998 | 1×1=1 | 0.42 | 5.2 | 265 | 521 | -- | 3.3 | 16 | 16 | 512-1024 | none |
| hyperSPARC D | 180–200 | V8 | 1996 | 1×1=1 | 0.35 | 1.7 | -- | -- | -- | 3.3 | 16 | 16 | 512 | none |
| UltraSPARC IIs (Blackbird) | 250–400 | V9 | 1997 | 1×1=1 | 0.35 | 5.4 | 149 | 521 | 25 @250 MHz | 2.5 | 16 | 16 | 1024 or 4096 | none |
| UltraSPARC IIs (Sapphire-Black) | 360–480 | V9 | 1999 | 1×1=1 | 0.25 | 5.4 | 126 | 521 | 21 @400 MHz | 1.9 | 16 | 16 | 1024–8192 | none |
| UltraSPARC IIi (Sabre) | 270–360 | V9 | 1997 | 1×1=1 | 0.35 | 5.4 | 156 | 587 | 21 | 1.9 | 16 | 16 | 256–2048 | none |
| UltraSPARC IIi (Sapphire-Red) | 333–480 | V9 | 1998 | 1×1=1 | 0.25 | 5.4 | -- | 587 | 21 @440 MHz | 1.9 | 16 | 16 | 2048 | none |
| UltraSPARC IIe (Hummingbird) | 400–600 | V9 | 2000 | 1×1=1 | 0.18 Al | -- | -- | 370 | 13 max @500 MHz | 1.5-1.7 | 16 | 16 | 256 | none |
| UltraSPARC IIi (IIe+) | 550–650 | V9 | 2002 | 1×1=1 | 0.18 Cu | -- | -- | 370 | 17.6 | 1.7 | 16 | 16 | 512 | none |
| UltraSPARC III (Cheetah) | 600 | V9 | 2001 | 1×1=1 | 0.18 Al | 29 | 330 | 1368 | 53 | 1.6 | 64 | 32 | 8192 | none |
| UltraSPARC III (Cheetah) | 750–900 | V9 | 2001 | 1×1=1 | 0.13 Al | 29 | -- | 1368 | -- | 1.6 | 64 | 32 | 8192 | none |
| UltraSPARC IIIcu (Cheetah+) | 1002–1200 | V9 | 2001 | 1×1=1 | 0.13 Cu | 29 | 232 | 1368 | 80 @900 MHz | 1.6 | 64 | 32 | 8192 | none |
| UltraSPARC IIIi (Jalepeno) | 1064–1593 | V9 | 2003 | 1×1=1 | 0.13 | 87.5 | 206 | 959 | 52 | 1.3 | 64 | 32 | 1024 | none |
| UltraSPARC IV (Jaguar) | 1050–1350 | V9 | 2004 | 1×2=2 | 0.13 | 66 | 356 | 1368 | 108 | 1.35 | 64 | 32 | 16384 | none |
| UltraSPARC IV+ (Panther) | 1500–1800 | V9 | 2005 | 1×2=2 | 0.09 | 295 | 336 | 1368 | 90 | 1.1 | 64 | 64 | 2048 | 32768 |
| UltraSPARC T1 (Niagara) | 1000–1200 | V9 / UA 2005 | 2005 | 4×8=32 | 0.09 | 300 | 380 | 1933 | 72 | 1.3 | 8 | 16 | 3072 | none |
[edit] SPARC64 V
SPARC64 V is a processor family developed by Fujitsu and used in their PRIMEPOWER family of servers.
[edit] Supercomputers
The fastest supercomputers based on SPARC64 processors:
- National Aerospace Laboratory of Japan. Machine: Fujitsu PRIMEPOWER HPC2500, CPU: 2304 SPARC64 (1.3 GHz). Rmax: 5.406 Teraflops.
[edit] See also
- UltraSPARC T1 – Sun's first multicore and multithread CPU (formerly known as "Niagara")
- UltraSPARC T2 – The successor to T1, taped out as of summer 2006.
- OpenSPARC – an open source project related to UltraSPARC T1
- ERC32 – based on SPARC V7 specification
- Rock processor – The follow on multi-processor version of T1, expected in 2008.
- Ross Technology, Inc. - SPARC designer/manufacturer of the 1980s and 1990s
[edit] External links
- SPARC International, Inc.
- SPARC Standards Documents Depository
- UltraSPARC Architecture specification - a SPARC architecture specification extended with CMT, hyperprivileged mode, VIS 1, VIS 2, and so forth
- UltraSPARC Processors
- SPARC processor images and descriptions
- The Rough Guide to MBus Modules (SuperSPARC, hyperSPARC)
- Open Directory: Computers: Hardware: Components: Processors: SPARC
[edit] BSD operating systems SPARC ports
- FreeBSD 64-bit SPARC Port
- NetBSD 32-bit SPARC Port
- NetBSD 64-bit SPARC Port
- OpenBSD 32-bit SPARC Port
- OpenBSD 64-bit SPARC Port
[edit] Linux distributions
- Gentoo Linux 64-bit SPARC Port
- Debian 32-bit and 64-bit SPARC Port
- Mandriva unofficial, unsupported SPARC Port
- Slackware 32-bit and 64-bit SPARC Port
- Ubuntu GNU/Linux support for UltraSPARC T1
- UltraLinux - Linux for SPARC processors
- Aurora SPARC Linux, unofficial Fedora SPARC port
| RISC |
|---|
| Power Architecture · ARM architecture · DEC Alpha · Atmel AVR · MIPS architecture · PA-RISC · PIC microcontroller · SPARC |
| Software: | Solaris • StarOffice/OpenOffice.org • Java Desktop System • Java (Java language • JVM • Java API) • JES • Network File System |
| Hardware: | SPARCstation • Sun Ultra series • Sun Enterprise • Sun Blade • Sun Fire • UltraSPARC T1 • SPARC • JavaStation • Sun Ray |
| Education and Recognition: | SCPs |
