Southbridge (computing)
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The Southbridge, also known as the I/O Controller Hub (ICH), is a chip that implements the "slower" capabilities of the motherboard in a northbridge/southbridge chipset computer architecture. The southbridge can usually be distinguished from the northbridge by not being directly connected to the CPU. Rather, the northbridge ties the southbridge to the CPU.
[edit] Overview
Because the southbridge is further removed from the CPU, it is given responsibility for the slower devices on a typical microcomputer. A particular southbridge will usually work with several different northbridges, but these two chips must be designed to work together; there is no industry wide standard for interoperability between different core logic chipset designs. Traditionally this interface between northbridge and southbridge was simply the PCI bus, however since this created a performance bottleneck, most current chipsets use a different (often proprietary) interface with higher performance.
[edit] Etymology
The name is derived from drawing the architecture in the fashion of a map. The CPU would be at the top of the map at due north. The CPU would be connected to the chipset via a fast bridge the northbridge located north of other system devices as drawn. The northbridge would then be connected to the rest of the chipset via a slow bridge (the southbridge) located south of other system devices as drawn.
[edit] Functionality
The functionality found on a contemporary southbridge includes:
- PCI bus
- ISA bus
- SMBus
- DMA controller
- Interrupt controller
- IDE (SATA or PATA) controller
- LPC Bridge
- Real Time Clock
- Power management (APM and ACPI)
- Nonvolatile BIOS memory
Optionally, the southbridge will also include support for Ethernet, RAID, USB, audio codec, and FireWire. Rarely, the southbridge may also include support for the keyboard, mouse, and serial ports, but normally these devices are attached through another device referred to as the Super I/O.
The PCI bus support includes the traditional PCI specification, but may also include support for PCI-X and PCI Express. Though the ISA support is rarely utilized, it has interestingly managed to remain an integrated part of the modern southbridge. The SMBus is used to communicate with other devices on the motherboard (e.g. system fans). The DMA controller allows ISA or LPC devices direct access to main memory without needing help from the CPU.
The interrupt controller provides a mechanism for attached devices to get attention from the CPU. The IDE interface allows direct attachment of system hard drives. The LPC Bridge provides a data and control path to the SIO (the normal attachment for the keyboard, mouse, parallel port, serial port, IR port, and floppy controller) and BIOS ROM (flash). The real time clock provides a persistent time account. The APM or ACPI functions provide methods and signaling to allow the computer to sleep or shut down to save power. The system CMOS, assisted by battery supplemental power, creates a limited non-volatile storage area for system configuration data.
