Serial Peripheral Interface Bus

From Wikipedia, the free encyclopedia

The Serial Peripheral Interface Bus or SPI (often pronounced like "spy") bus is a synchronous serial data link standard designed by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual select lines.

1 Interface
2 Operation
3 Applications
4 See also
5 External links

[edit] Interface

The SPI bus specifies four logic signals.

SCLK - Serial CLocK (output from master)
MOSI - Master Output, Slave Input (output from master)
MISO - Master Input, Slave Output (output from slave)
SS - Slave Select (active low) (output from master)

[edit] Operation

SPI Bus: Single Master / Single Slave

The SPI bus can operate with a single master device and with one or more slave devices. If a single slave device is used, the SS pin can be fixed to logic low. With multiple slave devices, a independent SS signal is required from the master for each slave device. Most devices have outputs that become high impedance (switched-off) when the device is not selected.

SPI Bus: Single Master / Multiple Slaves

To begin a communication, the master device generates a clock signal on SCLK. The master device activates a slave module by setting its respective SS line low. Data is transmitted to a slave device when SCLK goes low, and transmitted to the master when SCLK goes high. This arrangement permits several devices to talk to a single input. Clock speeds range from several kilohertz to several hundred megahertz.

[edit] Applications

The SPI full-duplex capability make it very simple and efficient for single master/single slave applications. The complexity of the interface grows as the number of slave devices increases due to its lack of built-in addressing. Some devices use the full-duplex mode to implement an efficient, high-speed data stream for applications such as digital audio, digital signal processing, or telecommunications channels.

In practice, many devices have exceptions. Some read data as SCLK goes high, and others read data as SCLK goes low. Sending data from slave to master is almost always during the opposite clock level as master to slave. Some devices have two clocks, one to "capture" or "display" data, and another to clock it into the device. Many of these "capture clocks" can be run from the SS line.