Talk:Reduced instruction set computer
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-- Rationalized Instruction Set? Was this an IEEE change? Who actually uses this definition?
Stanford doesn't. http://cse.stanford.edu/class/sophomore-college/projects-00/risc/risccisc/
In fact a google search reveals that only this Wiki entry uses it. I'm setting it back to the textbook definition.
So this a featured article? Wikipedia is ridiculous. --
By David Kanter
IBM's POWER architecture is used as the basis of the iSeries (formerly AS/400 midrange systems) and pSeries (formerly RS/6000). The IBM zSeries (formerly S/360,S/390 etc.) all run natively on a CISC chip that IS NOT POWER compatible at all.
-- "and the fastest CPU in SPECfp is the IBM Power 5 processor."
is ther a link to this benchmarks?
Removed:
- Pure RISC machines have failed in the general computer marketplace. They are not used in the majority of PCs or business computers. Notably, RISCs succeeded in digital signal processing and graphics computation. Because of these facts, many commentators believe that they failed in many applications because they have required larger, more expensive memory systems. Some RISC designers (Such as Acorn and IBM) have successfully responded to this criticism by producing RISC machines that decompress code on the fly.
Pure RISC machines have *not* failed in the marketplace, unless you count the PPC Macs as a failure. RISC architectures are used in virtually everything that isn't a x86 PC (including all virtually all the Unix servers out there). The reason why they didn't replace the x86 PC was that they didn't offer a compelling enough price-performance advantage (thanks partly to the sheer implementation skill of Intel) to warrant the extra costs and limited availability of OTS software and the lack of backward compability. --Robert Merkel
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Actually pure RISC has failed in the PC marketplace, as they make up less than 3% of the market and shrinking. While I think the original statement was over the top, the statements by Merkel are slightly short of the mark. Most unix servers are now linux servers powered by x86, and x86 now makes up the majority of the server market. And it's not price/performance that killed RISC on the PC, it's lack of software mainly; poor price/performance was a lesser drawback.
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I suggest the paragraph beginning with "This is surprising in view of the domination of the Intel x86..." be edited. Although I largely agree with the point presented, I feel the tone of the paragraph editorializes the matter.
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I greatly changed the pre-RISC section as it incorrectly discussed register set size as the main delimiter between RISC and CISC philosophies.
RISC Instruction Sets have failed in the marketplace, but not the design philosophy. Since all major x86 designs are very RISC-like internally (PentiumPro, Athlon), the design principles have affected all computer vendors.
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I removed the addition example; I had already made some copy-editing improvements to it, but it was still completely pointless IMHO. There was no attempt to connect the example to the rest of the article, or show why describing how addition works is relevant to RISC. I'm fine if someone wants to add it back, but please integrate it into the article with more care. -- Neilc 19:57, 25 Jul 2004 (UTC)
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Reading this article one would think that the IBM 390/zseries mainframes are built on Power RISC architecture hardware. This is incorrect. AFAIK, the IBM mainframes still execute the 360 ISA natively. Dyl 00:57, Oct 27, 2004 (UTC)
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- Some more practical-minded engineers now refer to RISC as "Relegate Important Stuff to the Compiler"
This is hardly a necessary remark unless the reasons behind it are clarified. The rest of the article doesn't seem to support it at all, even making points to the contrary ie. when discussing homogenous register sets.
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[edit] Section order incorrect
The "Pre-RISC design philosophy" section should precede the "RISC design philosophy" section --Surturz 07:41, 23 June 2006 (UTC)
[edit] RISC have more instructions than CISC
The statement "RISC is a computer CPU design philosophy that favors a smaller and simpler set of instructions" is actually a misnomer. While I am not intimately familiar with many RISC architectures, I do have significant experience with PowerPC and some exposure to MIPS. PowerPC documentation lists over 200 instructions and I believe that MIPS has even more. One consistancy that I have noticed among the RISC processors is that the instructions are typically of a fixed size, while CISC processors, such as the x86, tend to have variable length instructions. The result of this is that PowerPC code typically occupies more memory than functionally similar x86 code. The idea is that a fixed instruction size will result in a faster, more predictable, execution time, in general. -- jimwilliams57
- The term reduced in RISC refers more to a single instruction than to the entire set of instructions. While the set of instructions for a RISC may not be small, the amount of work that a single instruction accomplishes is reduced. This enables the hardware to treat instructions in a more uniform manner and benefits techniques like pipelining. A second point: If you count the instructions of an ISA with all possible modes (address modes, operand sizes, etc) the size of the PowerPC ISA is still small compared to x86. So the statement you criticize is probably still correct. --Stefan
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- No that is not what it refers to, RISC processors have a reduced instruction set, and thus the name is accurate. The design of MIPS or PowerPC does not negate the fact that most RISC processors have a smaller instruction set than most CISC processors.
- Read this: http://arstechnica.com/cpu/4q99/risc-cisc/rvc-4.html —The preceding unsigned comment was added by 68.118.218.191 (talk) 11:39, 11 December 2006 (UTC).
This is what I find confusing. A given RISC instruction accomplishes less and the difference is made up by running the clock faster.
- Sometimes. But part of the difference is also made up by the fact that a RISC CPU can execute more instructions per clock tick than a CISC CPU. 4.255.42.124 22:46, 3 September 2005 (UTC)
- You guys are focusing too much on small details. RISC really refers to a design philosophy that became popular with system designers because modern CPUs (known as CISC) were getting too difficult to build. By simplifying the hardware design using "RISC", they hoped to reduce the complexity and make designing more feasible and faster. This simplified design helped reduce die size which enabled additional functionality (like pipelines, register sets, cache, etc). This is what helped improved performance, not just the reduced instruction set. Improvements in compiler technology also played a part in RISC, it wasn't just hardware. --Pelladon 02:28, 8 July 2006 (UTC)
Yet advertised speeds for RISC chips are always slower than a comprable x86. Have I got it backwards or something?
- The problem of looking at just the clock rate is that while modern implementations of x86 such as the Pentium 4 run x86, they do not directly execute x86 instructions. Instead, each x86 instruction is translated at run-time into a short sequence of micro-ops, which are more like RISC instructions. This is done in order to support legacy programs, while taking advantage of the simplicity of a RISC implementation (in processor design, simpler usually means faster). Having said that, you might want to compare the execution time of a single RISC instruction to that of a single micro-op (In which case, keep reading :P).
- Another part of the answer has to do with pipelining, a technique all modern processors use. You can think of a single instruction as needing to go through every stage in a pipeline for it to be completely executed (this might not be exactly true if an instruction does not use the later stages in a pipeline). Each stage takes one cycle. A CISC which translates code into micro-ops usually has a much longer pipeline than a true RISC processor. For example, the Pentium 4 has a notoriously long pipeline of 20+ stages; whereas the classic RISC pipeline has only 5 stages. This means that a Pentium 4 running at 4Ghz executes a single (micro-op) instruction in the same time as a classical RISC does running only at 1Ghz. This is rather a trivial example though, because we are usually more concerned with instruction throughput (the rate of instructions coming out the end of the pipeline per unit time), rather than instruction latency. There are many factors that effect throughput.
- Danielx 21:38, 18 May 2006 (UTC)
The article also mentions that the 8086 has about 400 instructions. I would expect modern extensions of the architecture to have at least double that number. Comparatively, PowerPC easily counts as smaller and simpler.
[edit] This is the best article I have ever seen on wikipedia
This article explains the subject sooooo well, if only more math and science and articles can be this clear, especially in expounding the history and reasoning behind a development or innovation.
[edit] RISC = RNA induced silencing complex
i just run across this article in search for something completely different... i'm biology student and for me RISC means RNA induced silencing complex ... after some more searching i found it here: RNA-induced silencing complex but it is a little bit confusing not mentioning it on the RISC page. can we somehow crosslink this pages? or use RISC as abrevation page to point to the other two? --Damir Perisa 08:16, 15 September 2005 (UTC)
- I reckon RISC is more widely used as a computing term (I've never run into your use of the acronym before, but then I'm probably biased, being a CS student). I added a link to the page you mentioned, so both senses are now presented. --Lorkki 13:28, 18 September 2005 (UTC)
[edit] Berkeley RISC article
Some information here may belong in Berkeley RISC. Please discuss on Talk:Berkeley RISC#RISC article. StuartBrady 13:37, 12 January 2006 (UTC)
[edit] 6502 and Z80 comparison
I think that the comparison between the 6502 and the Z80 may be misleading. As far as I've been able to determine, a 6502 at 1 MHz and a Z80 at 4 MHz are similar performance, but it really depends on what you're doing. Instructions on the 6502 use fewer cycles... but you sometimes need to use more instructions (due to the lack of any 16-bit registers), and the 4MHz Z80 is clocked faster... Memory contention is a problem for Z80-based systems, but there are ways of mitigating the problem. Anyway, I'd like to see a more detailed study — I'm not saying the comparison is false, but I don't know that it's correct. --StuartBrady (Talk) 12:17, 5 July 2006 (UTC)
