Reconvergent fanout

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Reconvergent fanout is a technique to make VLSI logic simulation less pessimistic.

Static timing analysis tries to figure out the best and worst case time estimate for each signal as they pass through an electronic device. Whenever a signal passes through a node, a bit of uncertainty must be added to the time that required for the signal to transit that device. These uncertain delays up so, after passing through many devices, the worst-case timing for a signal will could be unreasonably pessimistic.

It is common for two signals share an identical path, branch and follow different paths for a while, then converge back to the same point to produce a result. When this happens, you can remove a fair amount of uncertainty from the total delay because you know that shared a common path for a while. Even though each signal has an uncertain delay, because their delays were identical for part of the journey (because they were in fact the same signal) the total uncertainty can be reduced. This tightens up the worst-case estimation for the signal delay, and usually allows a small but important speedup of the overall device.

There have been a number of papers written on reconvergent fanout but most, unfortunately, require IEEE or ACM subscriptions.

This term is starting to be used in a more generic sense as well. Any time a signal splits into two and then reconverges, certain optimizations can be made. The term "reconvergent fanout" has been used to describe similar optimizations in graph theory and static code analysis.

This page contains an example of reconvergent fanout: http://www.syncad.com/syn_time_analysis.htm