Quasi Delay Insensitive
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Quasi Delay Insensitive Circuits are a class of delay-insensitive asynchronous circuit which are invariant to (and make no assumptions about) the delays of any of the circuit's elements, except to assume that certain fanouts are isochronic forks. Isochronic forks allow signals to travel to two destinations and only receive an acknowledge from one. Isochronic forks are forks in wires where if the acknowledging target has seen a transition on their end of the fork then the transition must have also happened on the other end of the fork too. There are two types of isochronic forks; the asymmetric types only ensure that the signal will reach the acknowledging fork tip before, or at the same time as, it will at the other fork tip, while the symmetric type ensures that both fork tips will be reached at the same time. Symmetrical isochronic forks allow either of the targets to acknowledge the signal. In QDI circuits all forks have to be either isochronic and acknowledged by one of the destinations, or acknowledged by all destinations.
More importantly, QDI circuits are Turing-complete, while purely delay-insensitive circuits are not Turing-complete. So, of all "useful" asynchronous design styles, QDI circuits make the fewest timing assumptions, as only the isochronic fork is assumed. In practice ensuring the correctness of an isochronic fork is trivial.
(This is not true) The most common design style of QDI circuits is the DIMS Delay Insensitive Minterm Synthesis. (/This is not true)
The most common QDI design style today utilizes PCHBs (Precharge Half Buffers), approximately 90% of the Caltech MiniMIPS processors utilizes PCHB circuits. PCHBs are connected to form micro-pipelines and are similar to the pre-charged domino circuits used in the synchronous domain.
Several QDI microprocessors have been designed by compilation of message passing specifications into guarded commands. This includes the Caltech MiniMIPS processor which rivaled commercial MIPS implementations in performance, and worked over a larger range of supply voltages and temperatures.
The typical QDI design flow begins with a message passage specification in the form of CHP (Communicating Hardware Processes). CHP is a derivative of C.A. Hoare's CSP. A sequence of semantic preserving operations are applied to the CHP decomposing it into HSE (Handshaking Expansions). The HSE is reshuffled exposing concurrency and is then compiled into a PRS (Production Rule Set).
This strategy is inherently superior to the synchronous design flow as no timing assumptions need to be made at the architectural level and circuit correctness is guaranteed by construction. Isochronic forks and charge sharing problems must still be verified at the circuit level, but these are inherently simple problems to analyze and fix as they are local problems. Ultimately, this design style offers chip designers a better means of managing the complexity of the enormous system that is a 300+ million transistor processor. Finally, by removing timing assumptions transistors can be sized to optimize for speed or performance without altering the correctness of the system.
