QsNet II
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QsNetII is the latest generation of Quadrics Interconnect family products. Quadrics QsNetII interfaces to the host computer through the standard IO PCI-X bus.
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[edit] Architecture
The architecture of the network interface has been developed to offload the entire task of interprocessor communication from the main processor, and to avoid the overhead of system calls for user process to user process messaging. QsNetII is designed for use within SMP systems - multiple, concurrent processes can utilise the network interface without any task switching overhead. A I/O processor offloads protocol handling from the main CPU. Local memory on the PCI card provides storage for buffers, translation tables and I/O adapter code. All the PCI bandwidth is available to data communication.
[edit] Components
QsNetII's core design is based on two ASICs: Elan4 and Elite4. Elan4 is a communication processor that forms the interface between a high-performance multistage network and a processing node with one or more CPUs. Elite4 is a switching component that can switch eight bidirectional communications links, each of which carrying data in both directions simultaneously at 1.3 GBytes/s.
[edit] Topology
Quadrics QsNetII interconnect like its predecessor QsNet uses a 'fat tree' topology, QsNetII scales up to 4096 nodes, each node might have multiple CPUs so that systems of >10,000 CPUs to be constructed. Multiple, parallel QsNet networks can be employed in a system to maintain the compute to communications ratio where high CPU count SMP nodes are employed. The fat tree topology is resilient with large amounts of redundancy in the higher levels of the switch.
[edit] Latency and Bandwidth
Performance depends on platform used and configuration of the system, QsNetII MPI latency on standard AMD Opteron starts at 1.22 usec; Bandwidth on Intel Xeon EM64T is 912 Mbytes/s.
